Evaluation of a low - Cost column bump technology for fine pitch fip chip and WLP

Proceedings of the IEEE/CPMT International Electronics Manufacturing Technology (IEMT) Symposium

Volumn 29, Issue , 2004, Pages 18-21

  Gupta, D ^a   Kalle, F ^a   Fria, M ^a  

^a Adv Packaging/Syst Technol L LLC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASPECT RATIO; DIELECTRIC MATERIALS; ELECTROPLATING; MICROPROCESSOR CHIPS; SEMICONDUCTING GALLIUM ARSENIDE; SHOCK TESTING; THERMAL CYCLING;

FLIP CHIP PACKAGING; GOLD COLUMN BUMPS; METAL MASKS; SOLDER BUMPS;

FLIP CHIP DEVICES;

EID: 4644219566     PISSN: 10898190     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (27)

1. Gupta, D., "New Flip Chip Applications Drive Growth", p 11, Chip Scale Review, Sep 2003
2. Gupta, D. and Nagarkar M., 22Effect of process variables on the reflow and bonding of solder bumped flip chips", Proc. of 8 th Conference on Electronic Materials & Processes (1993), American Society of Materials International, Ohio, 1994, pp 83 - 90
3. Liu J. et al. "Electroless Nickel deposition on Al substrates", J. of Surface Finish, 1991
4. Gupta, D., "A novel active area bumped flip chip technology for convergent heat transfer from gallium arsenide power devices", Proc. 44 th ECTC, 1994, IEEE, pp 917 - 921 (also in Trans. IEEE CPMT, 1995)
5. Gupta, D., "A novel active area bumped flip chip technology for convergent heat transfer from gallium arsenide power devices", Proc. 44 th ECTC, 1994, IEEE, pp 917 - 921 (also in Trans. IEEE CPMT, 1995)
6. Gupta, D., "Evaluation of alternative processes for Au Sn - Au flip chip bonding of power devices", Proc. Intern'l Symp. on Microelectronics, ISHM, 1995, Los Angeles, pp 371 - 377 (also in ISHM Quarterly 1996)
7. Gupta, D., "Evaluation of alternative processes for Au Sn - Au flip chip bonding of power devices", Proc. Intern'l Symp. on Microelectronics, ISHM, 1995, Los Angeles, pp 371 - 377 (also in ISHM Quarterly 1996)
8. Suryanarayana, D., et al, "Flip chip solder bump fatigue life enhanced by polymer encapsulation", Proc. 40 th ECTC, IEEE, 1994, p 338 - 44
9. Giesler, J. et al, "Reliability of Flip Chip On Board assemblies", 1 st Int'l Symposium on Flip Chip Technology, San Jose, CA, 1994
10. Wong, C.P., et al, "Novel reworkable fluxing underfill for board level assembly", Proc. 53 rd ECTC, IEEE, p 940 - 45
11. Gross K., et al, "Nanocomposite underfills for flip chip applications", Proc. 52 nd ECTC, IEEE, 2003, p 951 - 56
12. Chee, C. K., et al., "Lead - free molded underfill technology for exposed die flip chip packages assembled in a molded matrix array packages form", Proc. 52 nd ECTC, IEEE, 2003, pp 962 - 970
13. Rahim, M. K., Suhling, J.C. et al., "Characterization of die stresses in flip chip laminate assemblies using (111) silicon stress chips", Proc. 40 th ECTC, IEEE, 2003, pp 905-919
14. Hurley, J.M., Berfield, T., "Underfill induced stresses in flip chip assemblies.", Proc. 40 th ECTC, IEEE, 2003, p 957-961
15. Wang G., T., Groothuis S., eta l., "Effect of packaging on interfacial cracking in Cu / low - k damascene structures", Proc. 53 rd ECTC, IEEE, 2003, pp 727 - 732.
16. Black, J. R.,: "Physics of Electromigration", Proc. IEEE, 1982
17. Choi, W. J., et al, "Electromigration of solder flip chip solder bump on Cu / Ni (V) / Al thin film under bump metallization", Proc. 52 nd ECTC, 2002, IEEE, pp 1201 - 1205.
18. Gan, H., et al, "Unique phase changes induced by electromigration (EM) in solder joints", Proc 53 rd ECTC, 2003, IEEE, pp 71 - 66
19. Adam, J.:"The 2003 ITRS Assembly & Packaging Roadmap", Int'l Technology Roadmap for Semiconductors, ITRS Workshop, Jul 2003, San Francisco
20. Bogatin, E., "Materials requirements for high performance digital systems", Circuitree, Aug 2003
21. Vandervelde, B., et al, "Optimal choice of the FEM damage volumes for estimation of the solder joint reliability for electronic package assemblies", Proc. 53 rd ECTC, 2003, IEEE, pp 589 - 96
22. Kalle, F., et al, paper in preparation
23. APSTL document, "Operation Manual for LCBP process line", 2001
24. Kim, N.S., Jung, S. Y. and Oh, S. Y., "Reliability of the Pb - free solder bump on electroless Ni under bump metallurgies", Proc. 53 rd ECTC, 2003, IEEE, pp 77 - 82.
25. Yau, E.W.C., Gong, J.F. et al, "A reliability comparison of lead free and eutectic solder for stencil printing based flip chip applications", Proc. 53 rd ECTC, 2003, IEEE, pp 323-330.
26. APSTL, "Bump structure and process for stress reduction and process therefor", US patent applied for, 2004
27. APSTL, "Apparatus and process for rapid plating in microscopic cavities", US patent applied for, 2004