Lead-free molded underfill technology for exposed die flip chip packages assembled in a molded matrix array packages form

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2003, Pages 962-970

  Chee, Choong Kooi ^a   Lim, Szu Shing ^a   Rudge, V A ^a   Periaman, Shanggar ^a   Ong, Ai Lin ^a   Chan, Hwa Wei ^a   Then, Edward ^a  

^a Intel Technology Malaysia Sdn Bhd   (Malaysia)

Author keywords

[No Author keywords available]

Indexed keywords

CRACKS; DEFECTS; DIES; ELECTRONICS PACKAGING; FILLERS; FILMS; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUIT TESTING; LEAD; MOLDING; RELIABILITY; STRESSES;

DIE FLIP CHIP PACKAGES; LEAD FREE MOLDED UNDERFILL; MOLDED MATRIX ARRAY PACKAGES FORM; RELIABILITY STRESS TEST; SUBSTRATE BLISTER;

FLIP CHIP DEVICES;

EID: 0037674593     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

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8. He, Y. "Thermal Characterization of Overmolded Underfill Materials for Stacked Chip Scale Packages" Proc. NATAS 2002.
9. Braun, T. et al., "Flip Chip Molding-High Reliable Flip Chip Encapsulation" Proc, 2002 ECTC