Low-power high-throughput BCH error correction VLSI design for multi-level cell NAND flash memories

2006 IEEE Workshop on Signal Processing Systems Design and Implementation, SIPS

Volumn , Issue , 2006, Pages 303-308

  Wei, Liu ^a   Junrye, Rho ^a   Wonyong, Sung ^a  

^a Seoul National University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

DECODING; ENCODING (SYMBOLS); ERROR CORRECTION; FLASH MEMORY; NAND CIRCUITS; SIGNAL PROCESSING; THROUGHPUT; VIDEO STREAMING;

APPLIED (CO); BCH ENCODER; BERLEKAMP-MASSEY ALGORITHMS; CHIP AREAS; CMOS TECHNOLOGIES; DECODER ARCHITECTURE; ECC SCHEME; ENCODER/DECODER; ERROR CORRECTION CODE (ECC); HIGH-THROUGHPUT (HT); KEY EQUATION; LOW POWERS; LOW-COMPLEXITY; MEMORY ACCESS TIME; MULTI LEVEL (ML); MULTILEVEL CELL (MLC) NAND; NAND FLASH MEMORIES; NEW GENERATION; POWER REDUCTIONS; RESOURCE SHARING; SIGNAL PROCESSING SYSTEMS; SUPPLY VOLTAGES; VLSI DESIGNS;

DATA STORAGE EQUIPMENT;

EID: 46249121123     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SIPS.2006.352599     Document Type: Conference Paper

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