-
1
-
-
0742321357
-
Fixed-outline floorplanning: Enabling hierarchical design
-
December
-
S. N. Adya and I. L. Markov. Fixed-outline floorplanning: Enabling hierarchical design. IEEE Trans, on VLSI Systems, 1(11):1120-1135, December 2003.
-
(2003)
IEEE Trans, on VLSI Systems
, vol.1
, Issue.11
, pp. 1120-1135
-
-
Adya, S.N.1
Markov, I.L.2
-
2
-
-
0031685684
-
The ISPD98 circuit benchmark suite
-
ACM, April
-
C. J. Alpert. The ISPD98 circuit benchmark suite. In Proc. ISPD'98, pages 80-85. ACM, April 1998.
-
(1998)
Proc. ISPD'98
, pp. 80-85
-
-
Alpert, C.J.1
-
3
-
-
54549117207
-
Faster optimal single-row placement with fixed ordering
-
ACM/IEEE, March
-
U. Brenner and J. Vygen. Faster optimal single-row placement with fixed ordering. In Proc. DATE'00, pages 117-121. ACM/IEEE, March 2000.
-
(2000)
Proc. DATE'00
, pp. 117-121
-
-
Brenner, U.1
Vygen, J.2
-
4
-
-
0034313430
-
Optimal partitioners and end-case placers for standard-cell layout
-
November
-
A. E. Caldwell, A. B. Kahng, and I. L. Markov. Optimal partitioners and end-case placers for standard-cell layout. IEEE Trans. on CAD of Integrated Circuits, 19(11):1304-1314, November 2000.
-
(2000)
IEEE Trans. on CAD of Integrated Circuits
, vol.19
, Issue.11
, pp. 1304-1314
-
-
Caldwell, A.E.1
Kahng, A.B.2
Markov, I.L.3
-
5
-
-
29144505066
-
Are floorplan representations important in digital design?
-
ACM, April
-
H. H. Chan, S. N. Adya, and I. L. Markov. Are floorplan representations important in digital design? In Proc. ISPD'05, pages 129-136. ACM, April 2005.
-
(2005)
Proc. ISPD'05
, pp. 129-136
-
-
Chan, H.H.1
Adya, S.N.2
Markov, I.L.3
-
6
-
-
0033701594
-
B*-trees: A new representation for non-slicing floorplans
-
ACM/IEEE, June
-
Y.-C. Chang, Y.-W. Chang, G.-M. Wu, and S.-W. Wu. B*-trees: a new representation for non-slicing floorplans. In Proc. DAC'00, pages 458-463. ACM/IEEE, June 2000.
-
(2000)
Proc. DAC'00
, pp. 458-463
-
-
Chang, Y.-C.1
Chang, Y.-W.2
Wu, G.-M.3
Wu, S.-W.4
-
7
-
-
29144499085
-
Modern floorplanning based on fast simulated annealing
-
ACM, April
-
T.-C. Chen and Y.-W. Chang. Modern floorplanning based on fast simulated annealing. In Proc. ISPD'05, pages 104-112. ACM, April 2005.
-
(2005)
Proc. ISPD'05
, pp. 104-112
-
-
Chen, T.-C.1
Chang, Y.-W.2
-
8
-
-
33751435863
-
IMF: Interconnect-driven multilevel floorplanning for large-scale building-module designs
-
ACM/IEEE, November
-
T.-C. Chen, Y.-W. Chang, and S.-C. Lin. IMF: Interconnect-driven multilevel floorplanning for large-scale building-module designs. In Proc. ICCAD'05, pages 159-164. ACM/IEEE, November 2005.
-
(2005)
Proc. ICCAD'05
, pp. 159-164
-
-
Chen, T.-C.1
Chang, Y.-W.2
Lin, S.-C.3
-
9
-
-
0032690067
-
An O-tree representation of non-slicing floorplan
-
ACM/IEEE, June
-
P.-N. Guo, C.-K. Cheng, and T. Yoshimura. An O-tree representation of non-slicing floorplan. In Proc. DAC'99,pages 268-273. ACM/IEEE, June 1999.
-
(1999)
Proc. DAC'99
, pp. 268-273
-
-
Guo, P.-N.1
Cheng, C.-K.2
Yoshimura, T.3
-
10
-
-
0034481271
-
-
X. Hong, G. Huang, Y. Cai, J. Gu, S. Dong, C. K. Cheng, and J. Gu. Corner block list: an effective and efficient topological representation of non-slicing floorplan. In Proc. ICCAD'00, pages 8-12. ACM/IEEE, November 2000.
-
X. Hong, G. Huang, Y. Cai, J. Gu, S. Dong, C. K. Cheng, and J. Gu. Corner block list: an effective and efficient topological representation of non-slicing floorplan. In Proc. ICCAD'00, pages 8-12. ACM/IEEE, November 2000.
-
-
-
-
11
-
-
0033705078
-
Classical floorplanning harmful?
-
ACM, April
-
A. B. Kahng. Classical floorplanning harmful? In Proc. ISPD'00, pages 207-213. ACM, April 2000.
-
(2000)
Proc. ISPD'00
, pp. 207-213
-
-
Kahng, A.B.1
-
12
-
-
33750904932
-
A tale of two nets: Studies of wirelength progression in physical design
-
ACM, March
-
A. B. Kahng and S. Reda. A tale of two nets: Studies of wirelength progression in physical design. In Proc. SLIP'06, pages 17-24. ACM, March 2006.
-
(2006)
Proc. SLIP'06
, pp. 17-24
-
-
Kahng, A.B.1
Reda, S.2
-
13
-
-
2942673331
-
Optimization of linear placements for wirelength minimization with free sites
-
ACM/IEEE, Janurary
-
A. B. Kahng, P. Tucker, and A. Zelikovsky. Optimization of linear placements for wirelength minimization with free sites. In Proc. ASP-DAC'99, pages 241-244. ACM/IEEE, Janurary 1999.
-
(1999)
Proc. ASP-DAC'99
, pp. 241-244
-
-
Kahng, A.B.1
Tucker, P.2
Zelikovsky, A.3
-
14
-
-
0032681035
-
Multilevel k-way hypergraph partitioning
-
ACM/IEEE, June
-
G. Karypis and V. Kumar. Multilevel k-way hypergraph partitioning. In Proc. DAC'99, pages 343-348. ACM/IEEE, June 1999.
-
(1999)
Proc. DAC'99
, pp. 343-348
-
-
Karypis, G.1
Kumar, V.2
-
16
-
-
0030378255
-
VLSI module placement based on rectangle-packing by the sequence pair
-
December
-
H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani. VLSI module placement based on rectangle-packing by the sequence pair. IEEE Trans. on CAD, 15(12):1518-1524, December 1996.
-
(1996)
IEEE Trans. on CAD
, vol.15
, Issue.12
, pp. 1518-1524
-
-
Murata, H.1
Fujiyoshi, K.2
Nakatake, S.3
Kajitani, Y.4
-
17
-
-
0026193508
-
Improvement of one dimensional module placement in VLSI layout design
-
July
-
M. Ohmura, S. Wakabayashi, J. Miyao, and N. Yoshida. Improvement of one dimensional module placement in VLSI layout design. Electronics and Communications in Japan, 74(7):67-76, July 1991.
-
(1991)
Electronics and Communications in Japan
, vol.74
, Issue.7
, pp. 67-76
-
-
Ohmura, M.1
Wakabayashi, S.2
Miyao, J.3
Yoshida, N.4
-
18
-
-
0032307685
-
Getting to the bottom of deep submicron
-
ACM, November
-
D. Sylvester and K. Keutzer. Getting to the bottom of deep submicron. In Proc. ICCAD'98, pages 203-211. ACM, November 1998.
-
(1998)
Proc. ICCAD'98
, pp. 203-211
-
-
Sylvester, D.1
Keutzer, K.2
-
19
-
-
0002701738
-
Fast evaluation of sequence pair in block placement by longest common subsequence computation
-
ACM/IEEE, March
-
X. Tang, R. Tian, and D. F. Wong. Fast evaluation of sequence pair in block placement by longest common subsequence computation. In Proc. DATE'00, pages 106-111. ACM/IEEE, March 2000.
-
(2000)
Proc. DATE'00
, pp. 106-111
-
-
Tang, X.1
Tian, R.2
Wong, D.F.3
|