A 75-GHz phase-locked loop in 90-nm CMOS technology

IEEE Journal of Solid-State Circuits

Volumn 43, Issue 6, 2008, Pages 1414-1426

  Lee, Jri ^a,b   Liu, Mingchung ^b   Wang, Huaide ^b  

^a IEEE

^b NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

Frequency divider; Phase and frequency detector (PFD); Phase locked loop (PLL); Reference spurs; Transmission line; Voltage controlled oscillator (VCO)

Indexed keywords

ARCHITECTURAL DESIGN; CMOS INTEGRATED CIRCUITS; COMPUTER NETWORKS; SPURIOUS SIGNAL NOISE; TECHNOLOGY;

CMOS TECHNOLOGIES; EXPERIMENTAL VERIFICATION; FEEDTHROUGH; HIGH FREQUENCY OPERATIONS; OPERATION RANGE; PHASE LOCKED LOOP (PLL); PHASE-FREQUENCY DETECTOR (PFD); QUARTER WAVELENGTH; REFERENCE SIDEBANDS; SINGLE SIDE-BAND (SSB) MIXERS;

PHASE LOCKED LOOPS;

EID: 44649199222     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2008.922719     Document Type: Article

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