A low-power adaptive bandwidth PLL and clock buffer with supply-noise compensation

IEEE Journal of Solid-State Circuits

Volumn 38, Issue 11, 2003, Pages 1804-1812

  Mansuri, Mozhgan ^a   Yang, Chih Kong Ken ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Adaptive bandwidth PLL; Low power analog circuits; Phase locked loops (PLLs); Self biased PLL; Timing jitter

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC INVERTERS; INTEGRATED CIRCUIT LAYOUT; MOSFET DEVICES; PHASE LOCKED LOOPS; SPURIOUS SIGNAL NOISE; TIMING CIRCUITS; TIMING JITTER; VARIABLE FREQUENCY OSCILLATORS;

ADAPTIVE BANDWIDTH PHASE LOCKED LOOP; CLOCK BUFFER; CURRENT CONTROLLED OSCILLATOR; PHASE FREQUENCY DETECTOR; PROGRAMMABLE CIRCUIT; VOLTAGE TO CURRENT CONVERTER;

ELECTRIC NETWORK SYNTHESIS;

EID: 0242720767     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2003.818300     Document Type: Article

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