A combined dynamic and static frequency divider for a 40GHz PLL in 80nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2006, Pages

  Von Büren, George ^a   Kromer, Christian ^a   Ellinger, Frank ^a   Huber, Alex ^b   Schmatz, Martin ^c   Jäckel, Heinz ^a  

^a ETH ZURICH   (Switzerland)

^b ZMA   (Switzerland)

^c IBM   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

FREQUENCY DIVIDING CIRCUITS; PHASE LOCKED LOOPS; SIGNAL ANALYSIS;

SIGNAL AMPLITUDES; STATIC FREQUENCY DIVIDERS;

CMOS INTEGRATED CIRCUITS;

EID: 39749184232     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. H. Knapp et al., "A 79GHz Dynamic Frequency Divider in SiGe Bipolar Technology," IEEE ISSCC Dig. Tech Papers, pp 208-209, Feb., 2000.
2. U. Singh and M. M. Green, "High-Frequency CML Clock Divider in 0.13nm CMOS Operating Up to 38GHz," IEEE J. Solid-State Circuits, vol. 40, pp 1658-1661, Aug., 2005.
3. J. Lee and B. Razavi, "A 40GHz Frequency Divider in 0.18μm CMOS Technology," IEEE J. Solid-State Circuits, vol. 39, pp 594-601, Apr., 2004
4. C. Kromer et al., "A 100mW 4×10Gb/s Transceiver in 80nm CMOS for High-density Optical Interconnects," IEEE J. Solid-State Circuits, vol. 40, pp 2667-2679, Dec., 2005.