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Volumn 29, Issue 5, 2008, Pages 474-476

High-performance nanowire TFTs with metal-induced lateral crystallized poly-Si channels

Author keywords

Metal induced lateral crystallization (MILC); Nanowires (NWs); Thin film transistors (TFTs); Triple gate structure

Indexed keywords

FIELD EFFECT SEMICONDUCTOR DEVICES; NANOWIRES; POLYSILICON; THRESHOLD VOLTAGE;

EID: 43549102427     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2008.920977     Document Type: Article
Times cited : (13)

References (16)
  • 1
    • 0002160997 scopus 로고
    • Cell design considerations for high-aperture-ratio direct-view and projection polysilicon TFT-LCDs
    • I. W. Wu, "Cell design considerations for high-aperture-ratio direct-view and projection polysilicon TFT-LCDs," in Proc. SID Dig. Tech. Papers, 1995, pp. 19-22.
    • (1995) Proc. SID Dig. Tech. Papers , pp. 19-22
    • Wu, I.W.1
  • 3
    • 0030129175 scopus 로고    scopus 로고
    • A high-performance polysilicon thin-film transistors using XeCl excimer laser crystallization of pre-patterned amorphous Si films
    • Apr
    • M. Cao, S. Talwar, K. J. Kramer, T. W. Sigmon, and K. C. Saraswat, "A high-performance polysilicon thin-film transistors using XeCl excimer laser crystallization of pre-patterned amorphous Si films," IEEE Trans. Electron Devices, vol. 43, no. 4, pp. 561-567, Apr. 1996.
    • (1996) IEEE Trans. Electron Devices , vol.43 , Issue.4 , pp. 561-567
    • Cao, M.1    Talwar, S.2    Kramer, K.J.3    Sigmon, T.W.4    Saraswat, K.C.5
  • 4
    • 0034250381 scopus 로고    scopus 로고
    • Super thin-film transistor with SOI CMOS performance formed by a novel grain enhancement method
    • Aug
    • H. Wang, M. Chan, S. Jagar, V. M. C. Poon, M. Qin, Y. Wang, and P. K. Ko, "Super thin-film transistor with SOI CMOS performance formed by a novel grain enhancement method," IEEE Trans. Electron Devices, vol. 47, no. 8, pp. 1580-1586, Aug. 2000.
    • (2000) IEEE Trans. Electron Devices , vol.47 , Issue.8 , pp. 1580-1586
    • Wang, H.1    Chan, M.2    Jagar, S.3    Poon, V.M.C.4    Qin, M.5    Wang, Y.6    Ko, P.K.7
  • 5
    • 0036683918 scopus 로고    scopus 로고
    • The effects of grain boundaries in the electrical characteristics of large grain polycrystalline thin-film transistor
    • Aug
    • V. W. C. Chan, P. C. H. Chan, and C. Yin, "The effects of grain boundaries in the electrical characteristics of large grain polycrystalline thin-film transistor," IEEE Trans. Electron Devices vol. 49, no. 8, pp. 1384-1391, Aug. 2002.
    • (2002) IEEE Trans. Electron Devices , vol.49 , Issue.8 , pp. 1384-1391
    • Chan, V.W.C.1    Chan, P.C.H.2    Yin, C.3
  • 6
    • 0036683921 scopus 로고    scopus 로고
    • An empirical model to determine the grain size of metal-induced lateral crystallized films
    • Aug
    • V. W. C. Chan and P. C. H. Chan, "An empirical model to determine the grain size of metal-induced lateral crystallized films," IEEE Trans. Electron Devices, vol. 49, no. 8, pp. 1399-1404, Aug. 2002.
    • (2002) IEEE Trans. Electron Devices , vol.49 , Issue.8 , pp. 1399-1404
    • Chan, V.W.C.1    Chan, P.C.H.2
  • 7
    • 33947375692 scopus 로고    scopus 로고
    • Effects of channel width on electrical characteristics of polysilicon TFTs with multiple nanowire channels
    • Oct
    • Y. C. Wu, T. C. Chang, P. T. Liu, C. S. Chen, C. H. Tu, H. W. Zan, Y. H. Tai, and C. Y. Chang, "Effects of channel width on electrical characteristics of polysilicon TFTs with multiple nanowire channels," IEEE Trans. Electron Devices, vol. 52, no. 10, pp. 2343-2346, Oct. 2005.
    • (2005) IEEE Trans. Electron Devices , vol.52 , Issue.10 , pp. 2343-2346
    • Wu, Y.C.1    Chang, T.C.2    Liu, P.T.3    Chen, C.S.4    Tu, C.H.5    Zan, H.W.6    Tai, Y.H.7    Chang, C.Y.8
  • 8
    • 33947244195 scopus 로고    scopus 로고
    • Fabrication and characterization of nanowire transistors with solid-phase crystallized poly-Si channel
    • Oct
    • H. C. Lin, M. H. Lee, C. J. Su, and S. W. Shen, "Fabrication and characterization of nanowire transistors with solid-phase crystallized poly-Si channel," IEEE Trans. Electron Devices, vol. 53, no. 10, pp. 2471-2477, Oct. 2006.
    • (2006) IEEE Trans. Electron Devices , vol.53 , Issue.10 , pp. 2471-2477
    • Lin, H.C.1    Lee, M.H.2    Su, C.J.3    Shen, S.W.4
  • 9
    • 2342652355 scopus 로고    scopus 로고
    • Triple-gate metal-oxide semiconductor field effect transistors fabricated with interference lithography
    • Apr
    • M. C. Lemme, C. Moormann, H. Lerch, M. Moller, B. Vratzor, and H. Kurz, "Triple-gate metal-oxide semiconductor field effect transistors fabricated with interference lithography," Nanotechnology, vol. 15, no. 4, pp. S208-S210, Apr. 2004.
    • (2004) Nanotechnology , vol.15 , Issue.4
    • Lemme, M.C.1    Moormann, C.2    Lerch, H.3    Moller, M.4    Vratzor, B.5    Kurz, H.6
  • 10
    • 29244445531 scopus 로고    scopus 로고
    • A new polysilicon CMOS self-aligned double-gate TFT technology
    • Dec
    • Z. Xiong, H. Liu, C. Zhu, and J. K. O. Sin, "A new polysilicon CMOS self-aligned double-gate TFT technology," IEEE Trans. Electron Devices, vol. 52, no. 2, pp. 2629-2633, Dec. 2005.
    • (2005) IEEE Trans. Electron Devices , vol.52 , Issue.2 , pp. 2629-2633
    • Xiong, Z.1    Liu, H.2    Zhu, C.3    Sin, J.K.O.4
  • 12
    • 36148986139 scopus 로고    scopus 로고
    • A simple spacer technique to fabricate poly-Si TFTs with 50-nm nanowire channels
    • Nov
    • C. W. Chang, C. K. Deng, H. R. Chang, C. L. Chang, and T. F. Lei, "A simple spacer technique to fabricate poly-Si TFTs with 50-nm nanowire channels," IEEE Electron Devices Lett., vol. 28, no. 11, pp. 993-995, Nov. 2007.
    • (2007) IEEE Electron Devices Lett , vol.28 , Issue.11 , pp. 993-995
    • Chang, C.W.1    Deng, C.K.2    Chang, H.R.3    Chang, C.L.4    Lei, T.F.5
  • 13
    • 84954157901 scopus 로고
    • Present and future trend of electron device technology in flat panel display
    • T. Uchida, "Present and future trend of electron device technology in flat panel display," in IEDM Tech. Dig., 1991, pp. 5-10.
    • (1991) IEDM Tech. Dig , pp. 5-10
    • Uchida, T.1
  • 14
    • 21044447633 scopus 로고    scopus 로고
    • On the feasibility of nanoscale triple-gate CMOS transistors
    • Jun
    • J. W. Yang and J. G. Fossum, "On the feasibility of nanoscale triple-gate CMOS transistors," IEEE Trans. Electron Devices, vol. 52, no. 6, pp. 1159-1164, Jun. 2005.
    • (2005) IEEE Trans. Electron Devices , vol.52 , Issue.6 , pp. 1159-1164
    • Yang, J.W.1    Fossum, J.G.2
  • 15
    • 0024739568 scopus 로고
    • Development and electrical properties of undoped polycrystalline silicon thin-film transistors
    • Sep
    • R. E. Proano, R. S. Misage, and D. G. Ast, "Development and electrical properties of undoped polycrystalline silicon thin-film transistors," IEEE Trans. Electron Devices, vol. 36, no. 9, pp. 1915-1922, Sep. 1989.
    • (1989) IEEE Trans. Electron Devices , vol.36 , Issue.9 , pp. 1915-1922
    • Proano, R.E.1    Misage, R.S.2    Ast, D.G.3
  • 16
    • 0034321619 scopus 로고    scopus 로고
    • An analytical model for current-voltage characteristics of a small-geometry poly-Si thin-film transistor
    • Nov
    • S. Chopra and R. S. Gupta, "An analytical model for current-voltage characteristics of a small-geometry poly-Si thin-film transistor," Semicond. Sci. Technol., vol. 15, no. 11, pp. 1065-1070, Nov. 2000.
    • (2000) Semicond. Sci. Technol , vol.15 , Issue.11 , pp. 1065-1070
    • Chopra, S.1    Gupta, R.S.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.