A coupled simulation and optimization approach to nanodevice fabrication with minimization of electrical characteristics fluctuation

2006 6th IEEE Conference on Nanotechnology, IEEE-NANO 2006

Volumn 1, Issue , 2006, Pages 12-15

  Li, Yiming ^a   Yu, Shao Ming ^a   Chen, Cheng Kai ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

Characteristics fluctuation; CMOS fabrication; Design; Modeling; Nanodevices; Optimization; Process and device simulation; Process recipe; Simulation; TCAD

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; INTELLIGENT SYSTEMS; OPTIMIZATION; VERIFICATION;

CHARACTERISTICS FLUCTUATION; CMOS FABRICATION; NANODEVICES;

NANOSTRUCTURES;

EID: 42549084764     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

1. N. Sano, A. Hiroki, K. Matsuzawa, "Device modeling and simulations toward sub-10 nm semiconductor devices," IEEE Transactions on Nanotechnology, vol. 1, pp. 63-71, 2002.
2. G. Pei et al., "FinFET design considerations based on 3-D simulation and analytical modeling," IEEE Trans. Elec. Dev., vol. 49, pp. 1411-1419, 2002.
3. S. Xiong and J. Bokor, "Sensitivity of Double-Gate and FinFET Devices to Process Variations" IEEE Trans. Elec. Dev., vol. 50, no. 11, pp. 2255-2261,2003.
4. F.-L. Yang et al., "5nm-gate nanowire FinFET" 2004 Symposium on VLSI Technology, pp. 15-17, 2004.
5. S. M. Ramey, and D. K. Ferry, "Modeling of quantum effects in ultrasmall FD-SOI MOSFETs with effective potentials and three-dimensional Monte Carlo," Physica B, vol. 314, pp. 350-353, March 2002.
6. Y. Li and S.-M. Yu, "A Unified Quantum Correction Model for Nanoscale Single- and Double-Gate MOSFETs under Inversion Conditions" Nanotechnology, vol. 15, no. 8, pp. 1009-1016, 2004.
7. Y. Li and S.-M. Yu, "Quantum correction simulation of random dopantinduced threshold voltage fluctuations in nanoscale metal- oxidesemiconductor structures" Proc. IEEE Nanotech. Conf., vol. 2, pp. 527-530, 2005.
8. A. Asenov et al., "Increase in the Random Dopant Induced Threshold Fluctuations and Lowering in Sub-100 nm MOSFETs Due to Quantum Effects: A 3-D Density-Gradient Simulation Study" IEEE Trans. Elec. Dev., vol. 48, no. 4, pp. 722-729, 2001.
9. K. A. Bowman et al., "Impact of extrinsic and intrinsic parameter fluctuations on CMOS circuit performance" Solid-State Circuits, vol. 35, no. 8, pp. 1186-1198, 2000.
10. S. Selberherr, Analysis and Simulation of Semiconductor Devices, New York: Springer-Verlag, 1984.
11. T. Binder et al., "A Study on Global and Local Optimization Techniques for TCAD Analysis Tasks", IEEE Trans. CAD, vol. 23, no. 6, pp. 814-822, 2004.
12. Y. Li et al., "Intelligent BSIM4 Model Parameter Extraction for Sub-100 nm MOSFET Era", Jpn. JAP, vol. 43, pp. 1717-1722, 2004.
13. Y. Li, et al., "Comparison of Random Dopant-Induced Threshold Voltage Fluctuations in Nanoscale Single-, Double, and Surrounding-Gate Field Effect Transistors," in Ext. Abs. 2005 Int. Conf. Solid State Devices and Materials, pp. 594-595, 2005.
14. Y. Li, et al., "A Novel Statistical Methodology for Sub-100 nm MOSFET Fabrication Optimization and Sensitivity Analysis," in Ext. Abs. 2005 Int. Conf. Solid State Devices and Materials, pp. 622-623, 2005.