Influence of extreme thinning on 130-nm standard CMOS devices for 3-D integration

IEEE Electron Device Letters

Volumn 29, Issue 4, 2008, Pages 322-324

  De Munck, Koen ^a   Chiarella, Thomas ^a   De Moor, Piet ^a   Swinnen, Bart ^a   Van Hoof, Chris ^a  

^a IMEC   (Belgium)

Author keywords

3 D integration; Chemical mechanical polishing (CMP); Gate leakage current; Grinding; Sheet resistance; Subsurface damage; Thin wafer transfer; Thinned device performance; Thinning; Thinning on carrier

Indexed keywords

CHEMICAL MECHANICAL POLISHING; GATES (TRANSISTOR); GRINDING (MACHINING); LEAKAGE CURRENTS; SHEET RESISTANCE; THREE DIMENSIONAL;

CMOS DEVICES; GATE LEAKAGE CURRENT; THIN WAFER TRANSFER; THINNED DEVICE PERFORMANCE; THINNING;

CMOS INTEGRATED CIRCUITS;

EID: 41749100136     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2008.917940     Document Type: Article

References (13)

1. J. D. Meindl, "Beyond Moore's law: The interconnect era," Comput. Sci. Eng., vol. 5, no. 1, pp. 20-24, Jan./Feb. 2003.
2. E. Beyne, "System driven approaches to 3D integration," in Proc. 4th Int. Symp. Microelectron. Packag., Seoul, South Korea, Sep. 28, 2005.
3. K. De Munck, L. Bogaerts, D. Sabuncuoglu Tezcan, P. De Moor, B. Swinnen, K. Baert, and C. Van Hoof, "Wafer level temporary bonding/debonding for thin wafer handling applications," in Proc. IMAPS Int. Conf. Exhib. Device Packag., Scottsdale, AZ, Mar. 2006.
4. K. De Munck, J. Vaes, L. Bogaerts, P. De Moor, C. Van Hoof, and B. Swinnen, "Grinding and mixed silicon copper CMP of stacked patterned wafers for 3D integration," in Proc. MRS Fall Meeting Symp. Y: Enabling Technol. 3D Integration, Boston, MA, Nov. 2006.
5. B. Swinnen, W. Ruythooren, P. De Moor, L. Bogaerts, L. Carbonell, K. De Munck, B. Eyckens, S. Stoukatch, D. Sabuncuoglu Tezcan, Z. Tokei, J. Vaes, J. Van Aelst, and E. Beyne, "3D integration by Cu-Cu thermo-compression bonding of extremely thinned bulk-Si die containing 10 μm pitch through-Si vias," in IEDM Tech. Dig., San Francisco, CA, Dec. 2006, pp. 371-374.
6. K. W. Guarini, A. W. Topol, M. Leong, R. Yu, L. Shi, M. R. Newport, D. J. Frank, D. V. Singh, G. M. Cohen, S. V. Nitta, D. C. Boyd, P. A. O'Neil, S. L. Tempest, H. B. Pogge, S. Purushothaman, and W. E. Haensch, "Electrical integrity of state-of-the-art 0.13 υm SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication," in IEDM Tech. Dig., San Francisco, CA, Dec. 2002, pp. 943-945.
7. R. J. Gutmann, J. Q. Lu, S. Devarajan, A. Y. Zeng, and K. Rose, "Wafer-level three-dimensional monolithic integration for heterogeneous silicon ICs," in Proc. Topical Meeting Silicon Monolithic Integr. Circuits RF Syst., Atlanta, GA, Sep. 8-10, 2004, pp. 45-48.
8. S. Pozder, J. Q. Lu, Y. Kwon, S. Zollner, J. Yu, J. J. McMahon, T. S. Cale, K. Yu, and R. J. Gutmann, "Back-end compatibility of bonding and thinning processes for a wafer-level 3D interconnect technology platform," in Proc. IITC Dig., 2004, pp. 102-104.
9. P. R. Morrow, C. M. Park, S. Ramanathan, M. J. Korinsky, and M. Harmes, "Three-dimensional wafer stacking via Cu-Cu bonding integrated with 65-nm strained-SiAow-k CMOS technology," IEEE Electron Device Lett. vol. 27, no. 5, pp. 335-337, May 2006.
10. F. Lepinois, S. Pinel, A. Cazarre, J. Tasselli, A. Marty, J.-P. Bailbe, J. R. Morante, F. Murray, and O. Gonnard, "Uhra-thinned chips integration: Technological approach and electrical qualification," in Proc. 23rd Int. Conf. Microelectron., 2002, vol. 2, pp. 521-524.
11. A. Ikeda, Y. Sugimoto, T. Kuwada, S. Kajiwara, T. Fujimura, K. Iwasaki, H. Ogi, K. Hamaguchi, H. Kuriyaki, R. Hattori, and Y. Kuroki, "A study of the reliability of MOSFETs in two stacked thin chips for 3D system in package," in Proc. 43rd Annu. IEEE Int. Rel. Phys. Symp., San Jose, CA, Apr. 17-21, 2005, pp. 578-579.
12. Online. Available: www.discousa.com/eg/products/catalog/Pdf/poligrind.pdf
13. C. Kasl and M. J. R. Hoch, "Effects of sample thickness on the van der Pauw technique for resistivity measurements," Rev. Sci. Instrum., vol. 76, no. 3, p. 033 907, Mar. 2005.