Grinding and mixed silicon copper CMP of stacked patterned wafers for 3D integration

Materials Research Society Symposium Proceedings

Volumn 970, Issue , 2007, Pages 275-280

  De Munck, Koen ^a   Vaes, Jan ^a   Bogaerts, Lieve ^a   De Moor, Piet ^a   Van Hoof, Chris ^a   Swinnen, Bart ^a  

^a IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

ADHESIVES; BONDING; COPPER; DELAMINATION; GRINDING (MACHINING);

CATASTROPHIC BREAKAGE; CMP TECHNIQUES; ENABLING TECHNOLOGIES; STACKED PATTERNED; THIN WAFER DELAMINATION;

WSI CIRCUITS;

EID: 34250825247     PISSN: 02729172     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. R.S. Patti, Proceedings of the IEEE, 94, 6, June (2006)
2. P. de Moor, 3-D Architectures for Semiconductor Integration and Packaging Conference, June (2005)
3. K. De Munck et al, IMAPS 2006 March 20-23, Scottsdale, USA
4. B. Swinnen et al, IEDM 2006 December 11-13, San Francisco, USA
5. J. Vaes et al, ICPT 2006 October 12-13, Foster City, USA
6. V. H. Nguyen, J. Electrochem. Soc. 150, G689 (2003)