A study of the reliability of mosfets in two stacked thin chips for 3D system in package

IEEE International Reliability Physics Symposium Proceedings

Volumn , Issue , 2005, Pages 578-579

  Ikeda, Akihiro ^a   Sugimoto, Yosuke ^a   Kuwada, Tomonori ^a   Kajiwara, Satoru ^a   Fujimura, Tsuyoshi ^a   Iwasaki, Kazuya ^b   Ogi, Hiroshi ^b   Hamaguchi, Kiyoshi ^b   Kuriyaki, Hisao ^a   Hattori, Reiji ^a   Kuroki, Yukinori ^a  

^a KYUSHU UNIVERSITY   (Japan)

^b Hara seiki Industry Co Ltd   (Japan)

Author keywords

Flip chip stacking; System in package; Wafer back grinding

Indexed keywords

EID: 28744439197     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. A. Ikeda, T. Kuwada, S. Kajiwara, T. Fujimura, H. Kuriyaki, R. Hattori, H. Ogi, K. Hamaguchi Y. Kuroki, " Design and Measurements of Test Element Group Wafer Thinned to 10μm for 3D System in Package" in Proc. IEEE Internal Conference on Microelectronic Test Structures, 2004, pp. 161-164.
2. T. S. Chen, Y. R. Huang, "Evaluation of MOS Devices as Mechanical Stress Sensors" IEEE Trans. on Components and Packaging technologies, Vol. 25, No. 3, 2002, pp.511-517.
3. A. T. Bradley, R. C. Jaeger, J. C. Suhling, K. J. O'Connor, "Piezoresistive Characteristics of Short-Channel MOSFETs on (100) Silicon" IEEE Trans. on Electron Devices, Vol. 48, No. 9, 2001, pp. 2009-2015.