Ultra-thinned chips integration: Technological approach and electrical qualification

2002 23rd International Conference on Microelectronics, MIEL 2002 - Proceedings

Volumn 2, Issue , 2002, Pages 521-524

  Lepinois F ^a   Pinel, S ^a   Cazarre A ^a   Tasselli, J ^a   Marty, A ^a   Bailbe J P ^a   Morante, J R ^b   Murray, F ^c   Gonnard, O ^a  

^a Laboratory for Analysis and Architecture of System   (France)

^b UNIVERSITY OF BARCELONA   (Spain)

^c NXP SEMICONDUCTORS   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; MICROELECTRONICS;

ADVANCED PACKAGING TECHNOLOGIES; CHIP SIZE PACKAGE; ELECTRICAL QUALIFICATION; ELECTRONICS SYSTEM; PORTABLE ELECTRONICS; ULTRA-THIN CHIPS; VERTICAL INTEGRATION; WEIGHT REDUCTION;

THREE DIMENSIONAL INTEGRATED CIRCUITS;

EID: 41749108675     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MIEL.2002.1003311     Document Type: Conference Paper

References (8)

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2. European patent EP1041620.
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4. De Graaff H.C., Gé rard de Groot J., The SIS Tunnel Emitter: A theory for emitters with thin interface layer. IEEE Trans Electron Devices 1979 ; ED26 :p. 1771-1776.
5. Austin P.,Caminade J.,Sanchez J.L. Technology and characterization of polysilicon emitter power bipolar transist ors. Solid State Electronics 1995; 38; 3: p. 587-598.
6. W. M. Gosney, "Subthreshold Drain Leakage Current in MOS Field-Effect Transistors ", IEEE Trans. Electron Devices, ED-19, 213 (1972).
7. A.C. Acheu, Dow Deutschland Inc., private communication.
8. Selberherr, INSPEC, "The Properties of Silicon ", EMIS vol.4 (IEE, 2nd ed. 1988).