-
1
-
-
4143109227
-
-
USA, Available at: 〈radhome.gsfc.nasa.gov/top.htm〉. Visitedon January, 2003
-
Nasa. Radiation Effects on Digital Systems. USA, 2002. Available at: 〈radhome.gsfc.nasa.gov/top.htm〉. Visitedon January, 2003.
-
(2002)
Radiation Effects on Digital Systems
-
-
-
3
-
-
0141521335
-
Scaling and Technology issues for soft error rates
-
Proceedings... Palo Alto: Stanford University, 2000
-
Johnston, A. Scaling and Technology Issues for Soft Error Rates, la Research Conference On Reliability, 4., 2000. Proceedings... Palo Alto: Stanford University, 2000.
-
(2000)
Research Conference on Reliability
, vol.4
-
-
Johnston, A.1
-
4
-
-
0037939810
-
Current single event effects and radiation damage results for candidate spacecraft electronics
-
Proceedings... [S.l.]: IEEE Computer Society, 2002
-
O'Bryan, M. et al. Current single event effects and radiation damage results for candidate spacecraft electronics. In IEEE Radiation Effects Data Workshop, 2002. Proceedings... [S.l.]: IEEE Computer Society, 2002. p. 82-105.
-
(2002)
IEEE Radiation Effects Data Workshop
, pp. 82-105
-
-
O'Bryan, M.1
-
5
-
-
0003217829
-
Applying computer simulation tools to radiation effects problems
-
Proceedings... [S.l.]: IEEE Computer Society, 1997
-
Barth, J. Applying Computer Simulation Tools to Radiation Effects Problems. In IEEE Nuclear Space Radiation Effects Conference, NSREC, 1997. Proceedings... [S.l.]: IEEE Computer Society, 1997. p. 1-83.
-
(1997)
IEEE Nuclear Space Radiation Effects Conference, NSREC
, pp. 1-83
-
-
Barth, J.1
-
6
-
-
0030349739
-
Single event upset at ground level
-
New York, Dec.
-
Normand, E. Single event upset at ground level. IEEE Transactions on Nuclear Science, New York, v.43, n.6, p. 2742-2750, Dec. 1996.
-
(1996)
IEEE Transactions on Nuclear Science
, vol.43
, Issue.6
, pp. 2742-2750
-
-
Normand, E.1
-
7
-
-
0036575107
-
Embedded robustness IPs for transient-error-free ICs
-
New York, May-June
-
Dupont, E.; Nicolaidis, M.; Rohr, P. Embedded robustness IPs for transient-error-free ICs. IEEE Design & Test of Computers, New York, v.19, n.3, p. 54-68, May-June 2002.
-
(2002)
IEEE Design & Test of Computers
, vol.19
, Issue.3
, pp. 54-68
-
-
Dupont, E.1
Nicolaidis, M.2
Rohr, P.3
-
8
-
-
84948970652
-
New methods for evaluating the impact of single event transients in VDSM ICs
-
Proceedings... [S.l.]: IEEE Computer Society, 2002
-
Alexandrescu, D.; Anghel, L.; Nicolaidis, M. New methods for evaluating the impact of single event transients in VDSM ICs. In: IEEE International Symposium On Defect And Fault Tolerance in VLSI Systems Workshop, DFT, 17., 2002. Proceedings... [S.l.]: IEEE Computer Society, 2002. p. 99-107.
-
(2002)
IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Workshop, DFT
, vol.17
, pp. 99-107
-
-
Alexandrescu, D.1
Anghel, L.2
Nicolaidis, M.3
-
9
-
-
0026393369
-
Upset due to a single particle caused propagated transient in a bulk CMOS microprocessor
-
New York, Dec.
-
Leavy, J. et al. Upset due to a single particle caused propagated transient in a bulk CMOS microprocessor. IEEE Transactions on Nuclear Science, New York, v.38, n.6, p. 1493-1499, Dec. 1991.
-
(1991)
IEEE Transactions on Nuclear Science
, vol.38
, Issue.6
, pp. 1493-1499
-
-
Leavy, J.1
-
10
-
-
8344275820
-
Probabilistic estimates of upset caused by single event transients
-
Proceedings... [S.l.: s.n.], 1999
-
Hass, J. Probabilistic Estimates of Upset Caused by Single Event Transients. In Nasa Symposium on VLSI Design, 8., 1999. Proceedings... [S.l.: s.n.], 1999.
-
(1999)
Nasa Symposium on VLSI Design
, vol.8
-
-
Hass, J.1
-
11
-
-
4143067088
-
-
Doctoral Thesis, Instituto de Informatica, UFRGS, Porto Alegre, Brazil
-
Guntzel, J.. Functional Timing Analysis of VLSI Circuits Containing Complex Gates, Doctoral Thesis, Instituto de Informatica, UFRGS, Porto Alegre, Brazil, 2001.
-
(2001)
Functional Timing Analysis of VLSI Circuits Containing Complex Gates
-
-
Guntzel, J.1
-
13
-
-
79955133275
-
Simulation-based analysis of SEU effects of SRAM-based FPGAs
-
Proceedings... [S.l.]: IEEE Computer Society, 2002
-
Rebaudengo, M.; Reorda, M.S.; Violante, M. Simulation-based Analysis of SEU effects of SRAM-based FPGAs. In International Workshop On Field-Programmable Logic And Applications, FPL, 2002. Proceedings... [S.l.]: IEEE Computer Society, 2002. p. 607-615.
-
(2002)
International Workshop on Field-Programmable Logic and Applications, FPL
, pp. 607-615
-
-
Rebaudengo, M.1
Reorda, M.S.2
Violante, M.3
-
14
-
-
70449989731
-
Single event upset in SRAM FPGAs
-
Proceedings... [S.l.: s.n.], 2002
-
Caffrey, M.; Graham, P.; Johnson, E. Single Event Upset in SRAM FPGAs, In Military and Aerospace Applications of Programmable Logic Conference, MAPLD, 2002. Proceedings... [S.l.: s.n.], 2002.
-
(2002)
Military and Aerospace Applications of Programmable Logic Conference, MAPLD
-
-
Caffrey, M.1
Graham, P.2
Johnson, E.3
-
16
-
-
0042193267
-
Testing of SEU mitigation methods for the Virtex® FPGA
-
Proceedings... [S.l.: s.n.], 2001
-
Carmichael, C.; Fuller, E.; Fabula, J.; Lima, F. Proton Testing of SEU Mitigation Methods for the Virtex® FPGA. In International Conference on Military and Aerospace Applications of Programmable Logic Devices, MAPLD, 2001. Proceedings... [S.l.: s.n.], 2001.
-
(2001)
International Conference on Military and Aerospace Applications of Programmable Logic Devices, MAPLD
-
-
Carmichael, C.1
Fuller, E.2
Fabula, J.3
Proton, L.F.4
-
17
-
-
0032296111
-
Neutron single event upsets in SRAM based FPGAs
-
Proceedings... [S.l.]: IEEE Computer Society, 1998
-
Ohlsson, M.; Dyreklev, P.; Johansson, K.; Alfke, P. Neutron Single Event Upsets in SRAM based FPGAs. In IEEE Nuclear Space Radiation Effects Conference, NSREC, 1998. Proceedings... [S.l.]: IEEE Computer Society, 1998.
-
(1998)
IEEE Nuclear Space Radiation Effects Conference, NSREC
-
-
Ohlsson, M.1
Dyreklev, P.2
Johansson, K.3
Alfke, P.4
-
18
-
-
0029216472
-
Circuit techniques for the radiation environment of space
-
Proceedings... [S.l.]: IEEE Computer Society, 1995
-
Canaris, J.; Whitaker, S. Circuit techniques for the radiation environment of space, In Custom Integrated Circuits Conference, 1995. Proceedings... [S.l.]: IEEE Computer Society, 1995, p. 77-80.
-
(1995)
Custom Integrated Circuits Conference
, pp. 77-80
-
-
Canaris, J.1
Whitaker, S.2
-
19
-
-
84944215733
-
Evaluation of a soft error tolerance technique based on time and/or space redundancy
-
SBCCI . Proceedings... Los Alamitos: IEEE Computer Society, 2000
-
Anghel, L.; Alexandrescu, D.; Nicolaidis, M. Evaluation of a soft error tolerance technique based on time and/or space redundancy. In Symposium on Integrated Circuits and Systems Design, SBCCI, 13., 2000. Proceedings... Los Alamitos: IEEE Computer Society, 2000. p. 237-242.
-
(2000)
Symposium on Integrated Circuits and Systems Design
, vol.13
, pp. 237-242
-
-
Anghel, L.1
Alexandrescu, D.2
Nicolaidis, M.3
-
21
-
-
0024169259
-
An SEU-hardened CMOS data latch design
-
New York, Dec.
-
Rockett, L. R. An SEU-hardened CMOS data latch design. IEEE Transactions on Nuclear Science, New York, v.35, n.6, p. 1682-1687, Dec. 1988.
-
(1988)
IEEE Transactions on Nuclear Science
, vol.35
, Issue.6
, pp. 1682-1687
-
-
Rockett, L.R.1
-
22
-
-
0026373079
-
SEU hardened memory cells for a CCSDS reed-solomon encoder
-
New York, Dec.
-
Whitaker, S.; Canaris, J.; Liu, K. SEU hardened memory cells for a CCSDS Reed-Solomon encoder. IEEE Transactions on Nuclear Science, New York, v.38, n.6, p. 1471-1477, Dec. 1991.
-
(1991)
IEEE Transactions on Nuclear Science
, vol.38
, Issue.6
, pp. 1471-1477
-
-
Whitaker, S.1
Canaris, J.2
Liu, K.3
-
23
-
-
0030375853
-
Upset hardened memory design for submicron CMOS technology
-
New York, Dec.
-
Calin, T.; Nicolaidis, M.; Velazco, R. Upset hardened memory design for submicron CMOS technology. IEEE Transactions on Nuclear Science, New York, v.43, n.6, p. 2874-2878, Dec. 1996.
-
(1996)
IEEE Transactions on Nuclear Science
, vol.43
, Issue.6
, pp. 2874-2878
-
-
Calin, T.1
Nicolaidis, M.2
Velazco, R.3
-
24
-
-
0023589974
-
An SEU tolerant memory cell derived from fundamental studies of SEU mechanisms in SRAM
-
New York, Dec.
-
Weaver, H.; et al. An SEU Tolerant Memory Cell Derived from Fundamental Studies of SEU Mechanisms in SRAM. IEEE Transactions on Nuclear Science, New York, v.34, n.6, Dec. 1987.
-
(1987)
IEEE Transactions on Nuclear Science
, vol.34
, Issue.6
-
-
Weaver, H.1
-
25
-
-
0035254416
-
A design based on proven concepts of an SEU-immune CMOS configurable data cell for reprogrammable FPGAs
-
Elsevier
-
Rockett, L. R. A design based on proven concepts of an SEU-immune CMOS configurable data cell for reprogrammable FPGAs. Microelectronics Journal, Elsevier, v.32, p. 99-111, 2001.
-
(2001)
Microelectronics Journal
, vol.32
, pp. 99-111
-
-
Rockett, L.R.1
-
27
-
-
0027577490
-
Multi-bit correcting data interface for fault-tolerant systems
-
New York, Apr.
-
Redinbo, G.; Napolitano, L.; Andaleon, D. Multi-bit Correcting Data Interface for Fault-Tolerant Systems. IEEE Transactions on Computers, New York, v.42, n.4, p. 433-446, Apr. 1993.
-
(1993)
IEEE Transactions on Computers
, vol.42
, Issue.4
, pp. 433-446
-
-
Redinbo, G.1
Napolitano, L.2
Andaleon, D.3
-
28
-
-
0142095226
-
A multiple bit upset tolerant SRAM memory
-
TODAES, New York, Oct.
-
Neuberger, G.; Lima, F.; Cairo, L.; Reis, R. A Multiple Bit Upset Tolerant SRAM Memory. Transactions on Design Automation of Electronic Systems, TODAES, New York, v.8, n.4, Oct. 2003.
-
(2003)
Transactions on Design Automation of Electronic Systems
, vol.8
, Issue.4
-
-
Neuberger, G.1
Lima, F.2
Cairo, L.3
Reis, R.4
-
32
-
-
0036995793
-
A fault injection analysis of Virtex FPGA TMR design methodology
-
RADECS . Proceedings... [S.l.]: IEEE Computer Society, 2001b
-
Lima, F.; Carmichael, C.; Fabula, J.; Padovani, R.; Reis, R. A fault injection analysis of Virtex FPGA TMR design methodology. In European Conference on Radiation and Its Effects on Components and Systems, RADECS, 2001. Proceedings... [S.l.]: IEEE Computer Society, 2001b. p. 275 -282.
-
(2001)
European Conference on Radiation and Its Effects on Components and Systems
, pp. 275-282
-
-
Lima, F.1
Carmichael, C.2
Fabula, J.3
Padovani, R.4
Reis, R.5
-
33
-
-
0031997904
-
A reliable fail-safe system
-
Feb.
-
Lubaszewski, M.; Courtois, B.; A reliable fail-safe system, IEEE Transactions on Computers, Volume: 47 Issue: 2, Feb. 1998, P. 236-241
-
(1998)
IEEE Transactions on Computers
, vol.47
, Issue.2
, pp. 236-241
-
-
Lubaszewski, M.1
Courtois, B.2
-
34
-
-
78751619530
-
Efficient use of time and hardware redundancy for concurrent error detection in a 32-bit VLSI adder
-
Feb.
-
Johnson, B.W., Aylor, J. H., Hana, H. Efficient Use of Time and Hardware Redundancy for Concurrent Error Detection in a 32-bit VLSI Adder. IEEE Journal of Solid-State-Circuits, pp. 208-215, Feb. 1988.
-
(1988)
IEEE Journal of Solid-state-circuits
, pp. 208-215
-
-
Johnson, B.W.1
Aylor, J.H.2
Hana, H.3
-
35
-
-
0042193265
-
Multiplier and divider arrays with concurrent error detection
-
Patel, J., Fung, L. Multiplier and Divider Arrays with Concurrent Error Detection, Proceedings of FTCS-25, Vol. 3, 1996.
-
(1996)
Proceedings of FTCS-25
, vol.3
-
-
Patel, J.1
Fung, L.2
-
36
-
-
0015160450
-
Arithmetic codes: Cost and effectiveness studies for applications in digital systems design
-
November
-
Avizienis, A. Arithmetic Codes: Cost and Effectiveness Studies for Applications in Digital Systems Design. IEEE Transaction on Computer, Vol. C-20, November, 1971.
-
(1971)
IEEE Transaction on Computer
, vol.C-20
-
-
Avizienis, A.1
|