Design based on proven concepts of an SEU-immune CMOS configuration data cell for reprogrammable FPGAs

Microelectronics Journal

Volumn 32, Issue 2, 2001, Pages 99-111

  Rockett, L R ^a  

^a LOCKHEED MARTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DIGITAL INTEGRATED CIRCUITS; FIELD PROGRAMMABLE GATE ARRAYS; INTEGRATED CIRCUIT LAYOUT;

SINGLE EVENT UPSET (SEU);

CMOS INTEGRATED CIRCUITS;

EID: 0035254416     PISSN: 00262692     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0026-2692(00)00134-8     Document Type: Article

References (13)

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