Impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits

International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 1996, Pages 237-242

  Eisele, M ^a   Berthold, J ^a   Schmitt Landsiedel, D ^a   Mahnkopf, R ^a  

^a TECHNICAL UNIVERSITY OF MUNICH   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; CMOS INTEGRATED CIRCUITS; ENERGY DISSIPATION; GEOMETRY; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUIT TESTING; SEMICONDUCTOR DOPING; TRANSISTORS;

SHORT CHANNEL EFFECT; STATISTICAL DEVIATIONS; THRESHOLD VOLTAGE;

DIGITAL CIRCUITS;

EID: 0029713734     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)