Quantifying the SMT layout overhead - Does SMT pull its weight?

IEEE High-Performance Computer Architecture Symposium Proceedings

Volumn , Issue , 2000, Pages 109-120

  Burns, James ^a   Gaudiot, Jean Luc ^a  

^a NORTHROP GRUMMAN CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; COMPUTER SIMULATION; ELECTRIC NETWORK ANALYSIS; INTEGRATED CIRCUIT LAYOUT; INTERCONNECTION NETWORKS; MICROPROCESSOR CHIPS; REDUCED INSTRUCTION SET COMPUTING; SEMICONDUCTING SILICON; TRANSISTORS;

INSTRUCTION SET ARCHITECTURE; MICROARCHITECTURE; SIMULTANEOUS MULTITHREADING;

PIPELINE PROCESSING SYSTEMS;

EID: 0034581565     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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