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Volumn , Issue , 2003, Pages

Dynamic scheduling issues in SMT architectures

Author keywords

[No Author keywords available]

Indexed keywords

DISTRIBUTED PARAMETER NETWORKS; MULTITASKING; PARALLEL PROCESSING SYSTEMS; PROGRAM PROCESSORS; SCHEDULING;

EID: 84947209298     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2003.1213179     Document Type: Conference Paper
Times cited : (11)

References (22)
  • 1
    • 84944725841 scopus 로고    scopus 로고
    • The simplescalar architectural research tool set
    • University ofWisconsin-Madison, June
    • T. Austin. The SimpleScalar Architectural Research Tool Set, Version 2. 0. Technical Report 1342, University ofWisconsin-Madison, June 1997.
    • (1997) Version 2. 0. Technical Report , vol.1342
    • Austin, T.1
  • 4
    • 0031237789 scopus 로고    scopus 로고
    • Simultaneous multithreading: A platform for next-generation processors
    • September/October
    • S. Eggers, J. Emer, H. Levy, J. Lo, R. Stamm, and D. Tullsen. Simultaneous Multithreading: A Platform for Next-Generation Processors. IEEE Micro, pages 12-18, September/October 1997.
    • (1997) IEEE Micro , pp. 12-18
    • Eggers, S.1    Emer, J.2    Levy, H.3    Lo, J.4    Stamm, R.5    Tullsen, D.6
  • 6
    • 0009361044 scopus 로고    scopus 로고
    • Dansoft develops vliwdesign
    • Feburary
    • L. Gwenlapp. Dansoft Develops VLIWDesign. Microprocessor Report, 11(2):18-22, Feburary 1997.
    • (1997) Microprocessor Report , vol.11 , Issue.2 , pp. 18-22
    • Gwenlapp, L.1
  • 7
    • 0034226001 scopus 로고    scopus 로고
    • SPEC CPU2000: Measuring CPU performance in the new millennium
    • July
    • J. Henning. SPEC CPU2000: Measuring CPU Performance in the New Millennium. IEEE Computer, 33(7):28-35, July 2000.
    • (2000) IEEE Computer , vol.33 , Issue.7 , pp. 28-35
    • Henning, J.1
  • 9
    • 84944750331 scopus 로고    scopus 로고
    • ALPSS: Architectural level power simulator for simultaneous multithreading
    • University of Southern California, April
    • S. Lee and J.-L. Gaudiot. ALPSS: Architectural Level Power Simulator for Simultaneous Multithreading, Version 1. 0. Technical Report TR-02-04, University of Southern California, April 2002.
    • (2002) Version 1. 0. Technical Report TR-02-04
    • Lee, S.1    Gaudiot, J.-L.2
  • 10
    • 0031199614 scopus 로고    scopus 로고
    • Converting thread-level parallelism to instruction-level parallelism via simultaneous multithreading
    • August
    • J. Lo, S. Eggers, J. Emer, H. Levy, R. Stamm, and D. Tullsen. Converting Thread-Level Parallelism to Instruction-Level Parallelism via Simultaneous Multithreading. ACM Transactions on Computer Systems, pages 322-354, August 1997.
    • (1997) ACM Transactions on Computer Systems , pp. 322-354
    • Lo, J.1    Eggers, S.2    Emer, J.3    Levy, H.4    Stamm, R.5    Tullsen, D.6
  • 11
    • 0034839064 scopus 로고    scopus 로고
    • Tolerating memory latency through software-controlled pre-execution in simultaneous multithreading processors
    • June
    • C. Luk. Tolerating Memory Latency through Software-Controlled Pre-Execution in Simultaneous Multithreading Processors. In Proceedings of the 28th Annual International Symposium on Computer Architecture, pages 40-51, June 2001.
    • (2001) Proceedings of the 28th Annual International Symposium on Computer Architecture , pp. 40-51
    • Luk, C.1
  • 12
    • 21144445427 scopus 로고    scopus 로고
    • Adaptively scheduling processes on a simultaneous multithreading processor
    • University of Wisconsin-Madison
    • M. McCormick, J. Ledlie, and O. Zaki. Adaptively Scheduling Processes on a Simultaneous Multithreading Processor. Technical report, University of Wisconsin-Madison, 2000.
    • (2000) Technical Report
    • McCormick, M.1    Ledlie, J.2    Zaki, O.3
  • 13
    • 0013229812 scopus 로고    scopus 로고
    • Thread-sensitive scheduling for SMT processors
    • University of Washington
    • S. Parekh, S. Eggers, H. Levy, and J. Lo. Thread-Sensitive Scheduling for SMT Processors. Technical report, University of Washington, 2000.
    • (2000) Technical Report
    • Parekh, S.1    Eggers, S.2    Levy, H.3    Lo, J.4
  • 22
    • 21144442242 scopus 로고    scopus 로고
    • Speculative precomputation: Exploring the use of multithreading for latency
    • Feburary
    • H. Wang, P. Wang, R. Weldon, and et. al. Speculative Precomputation: Exploring the Use of Multithreading for Latency. Intel Technology Journal, 6(1), Feburary 2002.
    • (2002) Intel Technology Journal , vol.6 , Issue.1
    • Wang, H.1    Wang, P.2    Weldon, R.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.