Low-K dielectric compatible wafer-level compliant chip-to-substrate interconnects

IEEE Transactions on Advanced Packaging

Volumn 31, Issue 1, 2008, Pages 22-32

  Kacker, Karam ^a   Lo, George C ^b   Sitaraman, Suresh K ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b Momentive Performance Materials Inc   (United States)

Author keywords

Chip to substrate interconnects; Compliant interconnects; First level interconnects; Low k dielectric; Wafer level packaging (WLP)

Indexed keywords

COST EFFECTIVENESS; DIELECTRIC MATERIALS; ELECTRONICS PACKAGING; INTEGRATED CIRCUIT MANUFACTURE; OPTIMIZATION; THERMAL EXPANSION;

OFF-CHIP INTERCONNECTS; WAFER LEVEL;

MICROELECTRONICS;

EID: 40549112358     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/TADVP.2007.908034     Document Type: Article

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