Development of G-Helix structure as off-chip interconnect

Journal of Electronic Packaging

Volumn 126, Issue 2, 2004, Pages 237-246

  Zhu, Qi ^a   Ma, Lunyu ^a   Sitaraman, Suresh K ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COSTS; DIELECTRIC MATERIALS; ELECTRONICS PACKAGING; ELECTROPLATING; FABRICATION; INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS; RELIABILITY; SEMICONDUCTOR MATERIALS; SILICON WAFERS; SOLDERING ALLOYS; STRAIN; STRESS CONCENTRATION;

G-HELIX INTERCONNECTS; OFF-CHIP INTERCONNECTS; SHEAR STRAIN;

OPTICAL INTERCONNECTS;

EID: 12344311066     PISSN: 10437398     EISSN: None     Source Type: Journal    
DOI: 10.1115/1.1756148     Document Type: Article

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