G-Helix: Lithography-based wafer-level compliant chip-to-substrate interconnects

Proceedings - Electronic Components and Technology Conference

Volumn 1, Issue , 2004, Pages 320-325

  Lo, George ^a   Sitaraman, Suresh K ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COEFFICIENT OF THERMAL EXPANSION (CTE); ELECTROPLATED STRUCTURES; GEOMETRIC PARAMETERS;

CHIP SCALE PACKAGES; COMPUTATIONAL GEOMETRY; COSTS; ELECTROPLATING; INTEGRATED CIRCUIT LAYOUT; LITHOGRAPHY; RELIABILITY; SELF ASSEMBLY; THERMAL EXPANSION;

LARGE SCALE SYSTEMS;

EID: 4544294892     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

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