SEVA: A soft-error- and variation-aware cache architecture

Proceedings - 12th Pacific Rim International Symposium on Dependable Computing, PRDC 2006

Volumn , Issue , 2006, Pages 47-54

  Hung, Luong D ^a   Goshima, Masahiro ^a   Sakai, Shuichi ^a  

^a UNIVERSITY OF TOKYO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; ERROR ANALYSIS; FAULT TOLERANCE; REDUNDANCY;

CACHE ARCHITECTURE; MEMORY CELLS; MEMORY HIERARCHY; SOFT ERRORS;

STATIC RANDOM ACCESS STORAGE;

EID: 40349087413     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PRDC.2006.56     Document Type: Conference Paper

References (17)

1. International Technology Roadmap for Semiconductor. http://public.itrs. net, 2005.
2. A. Agarwal, B. C. Paul, S. Mukhopadhyay, and K. Roy. Process Variation in Embedded Memories: Failure Analysis and Variation Aware Architecture. IEEE Journal on Solid State Circuits, 40(9):1804-1814, 2005.
3. R. Baumann. Soft Errors in Advanced Computer System. IEEE Design and Test of Computers, 22(3):258-266, 2005.
4. R. C. Baumann. Soft Errors in Advanced Semiconductor Devices-Part I: Three Radiation Sources. IEEE Transactions on Device and Materials Reliability, 1(1):17-22, 2001.
5. A. Benso, S. Chiusano, G. D. Natale, P. Prinetto, and M. L. Bodoni. A family of self-repair SRAM cores. In Proc. IEEE International On-Line Testing Workshop, pages 214-218, 2000.
6. A. Bhavnagarwala, S. Kosonocky, C. Radens, K. Stawiasz, R. Mann, Q. Ye, and K. Chin. Fluctuation Limits & Scaling Opportunities for CMOS SRAM Cells. In Proc. IEEE International Electron Devices Meeting, pages 659-662, 2005.
7. D. Burger and T. Austin. The SimpleScalar Tool Set. Technical Report CS-TR-1997-1342, University of WisconsinMadison, 1997.
8. D. J. Frank, Y. Taur, M. Ieong, and Hon. Monte Carlo Modelling of Threshold Variation due to Dopant Fluctuations. In Proc. IEEE International Electron Devices Meeting, pages 93-94, 1999.
9. H.-H. S. Lee, G. S. Tyson, and M. K. Farrens. Eager writeback - a technique for improving bandwidth utilization. In Proc. IEEE/ACM International Symposium on Microarchitecture, pages 11-21, 2000.
10. J. Maiz, S. Hareland, K. Zhang, and P. Armstrong. Characterization of Multi-bit Soft Error events in advanced SRAMs. In Proc. IEEE International Electron Devices Meeting, pages 519-522, 2003.
11. K. Osada, Y. Saitoh, and K. Ishibashi. 16.7-fA/Cell TunnelLeakage- Suppressed 16-Mb SRAM for Handling Cosmic Ray-Induced Multierrors. IEEE Journal on Solid State Circuits, 38(11):1952-1957, 2003.
12. V. Schober, S. Paul, and O. Picot. Memory Built-in SelfRepair using Redundant words. In Proc. IEEE International Test Conference, pages 995-1001, 2001.
13. C. H. Stapper and H.-S. Lee. Synergistic Fault-Tolerance for Memory Chips. IEEE Transactions on Computers, 41 (9): 1078-1088, 1992.
14. C-L. Su and Y-T. Yeh. An Integrated ECC and Redundancy Repair Scheme for Memory Reliability Enhancement. In Proc. IEEE International Test Conference, pages 81-89, 2005.
15. X. Tang, V. K. De, and J. D. Meindl. Intrinsic MOSFET Parameter Fluctuations Due to Random Dopant Placement. In Proc. IEEE International Electron Devices Meeting, pages 369-376, 1997.
16. T.R.N.Rao and E. Fujiwara. Error-Control Coding for Computer Systems. Prentice Hall, Inc, 1989.
17. Y. Zorian. Embedded infrastructure IP for SOC yield improvement. In Proc. IEEE/ACM Design Automation Conference, pages 709-712, 2002.