Key directions and a roadmap for electrical design for manufacturability

ESSDERC 2007 - Proceedings of the 37th European Solid-State Device Research Conference

Volumn 2007, Issue , 2007, Pages 83-88

  Kahng, Andrew B ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MATHEMATICAL MODELS; OPTIMIZATION; SEMICONDUCTOR DEVICES; STATISTICAL METHODS; VIRTUAL REALITY;

DFM TECHNOLOGIES; ELECTRICAL DESIGN; STATISTICAL OPTIMIZATION; VIRTUAL MANUFACTURING;

SYSTEMS ANALYSIS;

EID: 39549114053     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2007.4430885     Document Type: Conference Paper

References (28)

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2. A.B. Kahng and R.O. Topaloglu, "A TCAD-Based Study of Fill Pattern and Via Fill Impact on Low-k Dielectric Stress", invited paper, Proc. CMP-MIC, March 2007.
3. A.B. Kahng and R.O. Topaloglu, "A DOE Set for Normalization-Based Extraction of Fill Impact on Capacitances", Proc. ISQED, 2007.
4. A. B. Kahng, H. Wang and A. Zelikovsky, "Automated Layout and Phase Assignment Techniques for Dark Field Alternating PSM", Proc. BACUS Symposium on Photomask Technology and Management, Sept. 1998, pp. 222-231.
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6. P. Gupta, A. B. Kahng and P. Sharma, "Lithography Simulation-Based Full-chip Design Analyses", Proc. SPIE Conf. on Design and Process Integration for Microelectronic Manufacturing, 6156, 61560T (2006).
7. P. Gupta, A. B. Kahng, Y. Kim, S. Shah and D. Sylvester, "Modeling of Non-Uniform Device Geometries for Post-Lithography Circuit Analysis", Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing, 6156, 61560U (2006).
8. A. B. Kahng, C.-H. Park and X. Xu, "Fast Dual-Graph Based Hot-Spot Detection", Proc. 27th BACUS Symposium on Photomask Technology and Management, SPIE vol. 6281, 2006, p. 628104.
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