Design considerations for PD/SOI SRAM: Impact of gate leakage and threshold voltage variation

IEEE Transactions on Semiconductor Manufacturing

Volumn 21, Issue 1, 2008, Pages 33-40

  Kanj, Rouwaida ^a,b   Joshi, Rajiv V ^a,c   Sivagnaname, Jaykumaran ^a,b   Kuang, Jente B ^a,b   Acharyya, Dhruva ^b   Nguyen, Tuyet Y ^b   Nassif, Sani ^a,b  

^a IEEE

^b IBM AUSTIN RESEARCH LABORATORY   (United States)

^c IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Gate leakage; Reliability; SRAM; Stability; Yield estimation

Indexed keywords

ELECTRON TUNNELING; INFORMATION ANALYSIS; LEAKAGE CURRENTS; OPTIMIZATION; THRESHOLD VOLTAGE;

GATE LEAKAGE; MONITOR STRUCTURE; YIELD ESTIMATION;

STATIC RANDOM ACCESS STORAGE;

EID: 38949121920     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSM.2007.913189     Document Type: Conference Paper

References (17)

1. S. R. Nassif, "Design for variability in DSM technologies," in Proc. IEEE Int. Symp. Quality Electronic Design, 2000, pp. 451-454.
2. V. De and S. Borkar, "Technology and design challenges for low power and high performance," in IEEE Int. Symp. Low Power Design, 1999, pp. 163-168.
3. R. V. Joshi et al., "Variability analysis for sub-100 nm PD/SOI CMOS SRAM cell," in Proc. 30th Eur. Solid State Cricuits Conf., 2004, pp. 211-214.
4. D. Burnett et al., "Implications of fundamental threshold voltage variations for high-density SRAM and logic circuits," in Proc. Symp. VLSI Technology, 1994, pp. 7-9.
5. A. B. Hoenseisen and C. A. Mead, "Localized variability: Random dopant fluctuations," J. Solid State Circuits, 1972.
6. J. C. Lee, I. Chen, and C. Hu, "Modeling and characterization of gate oxide reliability," IEEE Trans. Electron Devices, vol. 35, no. 12, pp. 2268-2278, Dec. 1988.
7. R. Kanj et al., "Gate leakage effects on yield and design considerations of PD/SOI SRAM designs," in Proc. Int. Symp. Quality Electronic Design, 2006, pp. 33-40.
8. R. V. Joshi et al., "Effects of gate-to-body tunneling current on PD/SOI CMOS SRAM," in Proc. Symp. VLSI Technology, 2001, pp. 75-78.
9. F. Liu, "Method and apparatus for measuring device mismatches," U.S. patent application 11/422913.
10. BSIM Models [Online], Available: http://www.device.eecs.berkeley.edu/ ~bsimsoi
11. W. G. Cochran, Sampling Techniques, 3rd ed. New York: Wiley, 1977.
12. T. C. Hesterberg, "Advances in importance sampling," Ph.D. dissertation, Statistics Department, Stanford Univ., Stanford, CA, 1988.
13. D. E. Hocevar, M. R. Lightner, and T. N. Trick, "A study of variance reduction techniques for estimating circuit yields," IEEE Trans. Comput.-Aided Design, vol. 2, no. 7, pp. 180-192, Jul. 1983.
14. R. Kanj, R. Joshi, and S. Nassif, "Mixture importance sampling and its application to the analysis of SRAM designs in die presence of rare failure events," in Proc. IEEE Design Automation Conf. 2006, pp. 64-67.
15. R. Joshi et al., "Statistical exploration of the dual supply voltage space of a 65 nm. PD/SOI CMOS SRAM cell," in Proc. Eur. Solid State Device Research Conf., 2006, pp. 315-318.
16. J. Davis et al., "A 5.6 GHz 64 kB dual-read data cache for the POWER6™ processor," in Proc. IEEE Int. Conf. Solid-State Circuits, 2006, pp. 33-34.
17. J. Pille et al., "Implementation of the CELL broadband engine in a 65 nm SOI technology featuring dual-supply SRAM arrays supporting 6 GHz at 1.3 V," in Proc. IEEE Int. Conf. Solid-State. Circuits, 2007, pp. 322-323.