Gate leakage effects on yield and design considerations of PD/SOI SRAM designs

Proceedings - Eighth International Symposium on Quality Electronic Design, ISQED 2007

Volumn , Issue , 2007, Pages 33-38

  Kanj, Rouwaida ^a   Joshi, Rajiv ^b   Sivagnaname, Jayakumaran ^a   Kuang, J B ^a   Acharyya, Dhruva ^a   Nguyen, Tuyet ^a   McDowell, Chandler ^a   Nassif, Sani ^a  

^a IBM AUSTIN RESEARCH LABORATORY   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRON TUNNELING; GATES (TRANSISTOR); LEAKAGE CURRENTS; LOGIC DESIGN; OPTIMIZATION;

GATE-LEAKAGE IMPACTS; GATE-LEAKAGE TUNNELING CURRENTS; HARDWARE MEASUREMENTS;

STATIC RANDOM ACCESS STORAGE;

EID: 34548118644     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2007.83     Document Type: Conference Paper

References (10)

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