On the calibration of abstract performance models for system-level design space exploration

Proceedings - 2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2006

Volumn , Issue , 2006, Pages 71-77

  Pimentel, Andy D ^a   Thompson, Mark ^a   Polstra, Simon ^a   Erbas, Cagkan ^a  

^a UNIVERSITY OF AMSTERDAM   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

EMBEDDED SYSTEMS; INTEGRATED CIRCUITS; SYSTEMS ANALYSIS;

DESIGN SPACE EXPLORATION; HIGH-LEVEL MODELING; PERFORMANCE ESTIMATION; PERFORMANCE MODEL; PERFORMANCE MODELING AND SIMULATION; SYSTEM LEVEL DESIGN; SYSTEM LEVEL SIMULATION; SYSTEM-LEVEL PERFORMANCE;

COMPUTER ARCHITECTURE;

EID: 38849104915     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICSAMOS.2006.300811     Document Type: Conference Paper

References (25)

1. K. Keutzer, S. Malik, A. Newton, J. Rabaey, and A. Sangiovanni- Vincentelli, "System level design: Orthogonalization of concerns and platform-based design," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 12, Dec. 2000.
2. F. Balarin, E. Sentovich, M. Chiodo, P. Giusto, H. Hsieh, B. Tabbara, A. Jurecska, L. Lavagno, C. Passerone, K. Suzuki, and A. Sangiovanni-Vincentelli, Hardware-Software Co-design of Embedded Systems - The POLIS approach. Kluwer Academic Publishers, 1997.
3. F. Balarin, Y. Watanabe, H. Hsieh, L. Lavagno, C. Passerone, and A. Sangiovanni-Vincentelli, "Metropolis: An integrated electronic system design environment," IEEE Computer, vol. 36, no. 4, April 2003.
4. A. Cassidy, J. Paul, and D. Thomas, "Layered, multi-threaded, high-level performance design," in Proc. of the Design, Automation and Test in Europe (DATE), March 2003.
5. V. Mathur and V. Prasanna, "A hierarchical simulation framework for application development on system-on-chip architectures," in IEEE Intl. ASIC/SOC Conference, Sept. 2001.
6. J. E. Coffland and A. D. Pimentel, "A software framework for efficient system-level performance evaluation of embedded systems," in Proc. of the ACM Symp. on Applied Computing (SAC), March 2003, pp. 666-671, http://sesamesim.sourceforge.net/.
7. A. D. Pimentel, C. Erbas, and S. Polstra, "A systematic approach to exploring embedded system architectures at multiple abstraction levels," IEEE Transactions on Computers, vol. 55, no. 2, pp. 99-112, 2006.
8. T. Kogel, A. Wieferink, R. Leupers, G. Ascheid, H. Meyr, D. Bussaglia, and M. Ariyamparambath, "Virtual architecture mapping: A SystemC based methodology for architectural exploration of system-on-chip designs," in Proc. of the Int. workshop on Systems, Architectures, Modeling and Simulation (SAMOS), 2003, pp. 138-148.
9. B. Kienhuis, E. F. Deprettere, K. A. Vissers, and P. van der Wolf, "An approach for quantitative analysis of application-specific dataflow architectures," in Proc. of the IEEE Int. Conference on Application-specific Systems, Architectures and Processors, July 1997.
10. G. Kahn, "The semantics of a simple language for parallel programming," in Proc. of the IFIP Congress 74, 1974.
11. A. Turjan, B. Kienhuis, and E. F. Deprettere, "Translating affine nested loop programs to process networks," in Proc. of the Int. Conf. on Compilers, Architectures and Synthesis for Embedded Systems (CASES), Sept. 2004.
12. T. Stefanov, C. Zissulescu, A. Turjan, B. Kienhuis, and E. F. Deprettere, "System design using Kahn process networks: The Compaan/Laura approach," in Proc. of the Int. Conference on Design, Automation and Test in Europe (DATE), Feb. 2004, pp. 340-345.
13. A. D. Pimentel and C. Erbas, "An IDF-based trace transformation method for communication refinement," in Proc. of the ACM/IEEE Design Automation Conference, June 2003, pp. 402-407.
14. T. Austin, E. Larson, and D. Ernst, "Simplescalar: An infrastructure for computer system modeling," IEEE Computer, vol. 35, no. 2, pp. 59-67, Feb. 2002.
15. A. D. Pimentel, M. Thompson, S. Polstra, and C. Erbas, "Trace calibration: A mixed-level co-simulation technique for system-level design space exploration," Unpublished, submitted for publication, see also http://www.science,uva.nl/∼andy/trace_cal.pdf.
16. C. Zissulescu, T. Stefanov, B. Kienhuis, and E. F. Deprettere, "LAURA: Leiden architecture research and exploration tool," in Proc. 13th Int. Conference on Field Programmable Logic and Applications (FPL), Sept. 2003.
17. T. Stefanov, B. Kienhuis, and E. F. Deprettere, "Algorithmic transformation techniques for efficient exploration of alternative application instances," in Proc. of the Int. Symposium on Hardware/Software Codesign (CODES), May 2002, pp. 7-12.
18. S. Vassiliadis, S. Wong, G. N. Gaydadjiev, K. Bertels, G. Kuzmanov, and E. M. Panainte, "The Molen polymorphic processor," IEEE Transactions on Computers, vol. 53, no. 11, pp. 1363-1375, Nov. 2004.
19. B. Black and J. P. Shen, "Calibration of microprocessor performance models," IEEE Computer, vol. 31, no. 5, pp. 59-65, 1998.
20. M. Moudgill, J.-D. Wellman, and J. H. Moreno, "Environment for PowerPC microarchitecture exploration," IEEE Micro, vol. 19, no. 3, pp. 15-25, 1999.
21. J.-Y. Brunei, W. M. Kruijtzer, H. J. Kenter, F. Pétrot, L. Pasquier, E. A. de Kock, and W. J. M. Smits, "COSY communication IP's," in Proc. of the ACM/IEEE Design Automation Conference, 2000, pp. 406-409.
22. P. Giusto, G. Martin, and E. Harcourt, "Reliable estimation of execution time of embedded software," in Proc. of the conference on Design, Automation and Test in Europe (DATE), 2001, pp. 580-589.
23. J. Calvez, D. Heller, and O. Pasquier, "Uninterpreted co-simulation for performance evaluation of hw/sw systems," in Proc. of the Int. Workshop on Hardware-Software Co-Design, 1996, pp. 132-139.
24. A. Baghdadi, N.-E. Zergainoh, W. Cesario, T. Roudier, and A. A. Jerraya, "Design space exploration for hardware/software codesign of multiprocessor systems," in IEEE International Workshop on Rapid System Prototyping, 2000, pp. 8-13.
25. L. Cai and D. Gajski, "Transaction level modeling: An overview," in Proc. of the Int. Conference on HW/SW Codesign and System Synthesis (CODES-ISSS), Oct. 2003, pp. 19-24.