Scalable model of on-wafer interconnects for high-speed CMOS ICs

IEEE Transactions on Advanced Packaging

Volumn 29, Issue 4, 2006, Pages 770-776

  Shi, Xiaomeng ^a   Yeo, Kiat Seng ^a   Ma, Jian Guo ^a   Do, Manh Anh ^a,b   Li, Erping ^c  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^b UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA   (China)

^c INSTITUTE OF HIGH PERFORMANCE COMPUTING   (Singapore)

Author keywords

CMOS interconnects; Empirical formulas; Lumped equivalent circuit model; Particle swarm optimization; Scalable; Scattering parameter measurements

Indexed keywords

ALGORITHMS; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION; WSI CIRCUITS;

COMPUTER-AIDED DESIGN TOOLS; EQUIVALENT CIRCUIT MODEL; HIGH-SPEED CMOS ICS; ON-WAFER INTERCONNECTS; PARTICLE SWARM OPTIMIZATION;

CMOS INTEGRATED CIRCUITS;

EID: 37849185056     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/TADVP.2006.884781     Document Type: Article

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