Design issues in next-generation merchant switch fabrics

IEEE/ACM Transactions on Networking

Volumn 15, Issue 6, 2007, Pages 1603-1615

  Abel, François ^a   Minkenberg, Cyriel ^a   Iliadis, Ilias ^a   Engbersen, Ton ^a   Gusat, Mitchell ^a   Gramsamer, Ferdinand ^a,b   Luijten, Ronald P ^a  

^a IBM RESEARCH ZURICH   (Switzerland)

^b Software Services Corporation   (Switzerland)

Author keywords

Application specific integrated circuits; Buffered crossbar; Combined Input and Crosspoint Queueing (CICQ); Interconnection networks; Multiprocessor interconnection; packet switching; Storage area networks

Indexed keywords

BUFFER STORAGE; COMPUTER NETWORKS; INTEGRATED CIRCUITS; INTERCONNECTION NETWORKS;

BUFFERED CROSSBAR; COMBINED INPUT-AND CROSSPOINT QUEUEING; STORAGE AREA NETWORKS;

PACKET SWITCHING;

EID: 37549015943     PISSN: 10636692     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNET.2007.909727     Document Type: Article

References (42)

1. F. M. Chiussi, J. G. Kneuer, and V. P. Kumar, "Low-cost scalable switching solution for broadband networking: The ATLANTA architecture and chipset," IEEE Commun. Mag., vol. 35, no. 3, pp. 44-45, Dec. 1997.
2. J. Turner and N. Yamanaka, "Architectural choices in large scale ATM switches," IEICE Trans. Commun., vol. E81-B, no. 2, pp. 120-137, 1998.
3. J. Bolaria and B. Wheeler, A Guide To Switch Fabrics. Mountain View, CA: The Linley Group, 2002.
4. J. Duato, S. Yalamanchili, and L. Ni, Interconnection Networks, An Engineering Approach. San Francisco, CA: Morgan Kaufmann, 2003.
5. Standard for Local and Metropolitan Area Networks: Overview and Architecture, IEEE Std 802-2001, LAN/MAN Standards Committee, IEEE Computer Society, Feb. 2002.
6. S. Floyd and V. Paxson, "Difficulties in simulating the Internet," IEEE/ACM Trans. Networking, vol. 9, no. 4, pp. 392-403, Aug. 2001.
7. Infiniband Architecture, Specification 1.0.a, Jun. 19, 2001.
8. F. Baker, "Requirements for IP version 4 routers," IETF RFC 1812, Jun. 1995.
9. C. Berger, M. Kossel, C. Menolfi, T. Morf, T. Toifl, and M. Schmatz, "High-density optical interconnects within large-scale systems," Proc. SPIE, vol. 4942, pp. 222-235, 2003.
10. W. Ng, P. Galloway, and M. Annand, "Copper cabling for multi-gigabit serial links for inter-cabinet connections," in Proc. High Performance System Design Conf. (DesignCon2002), Santa Clara, CA, Jan. 2002.
11. P. Chiang, W. J. Dally, and M.-J. E. Lee, "A 20 Gb/s 0.13 μm CMOS serial link," in Proc. Hot Chips 2002, 14th Symp. High Performance Chips, Palo Alto, CA, Aug. 2002.
12. R. Ronen, A. Mendelson, K. Lai, S.-L. Lu, F. Pollack, and J. P. Shen, "Coming challenges in microarchitecture and architecture," Proc. IEEE, vol. 89, no. 3, pp. 325-340, Mar. 2001.
13. H. C. C. Chan, H. M. Alnuweiri, and V. C. M. Leung, "A framework for optimizing the cost and performance of next-generation IP routers," IEEE J. Sel. Areas Commun., vol. 17, no. 6, pp. 1013-1029, Jun. 1999.
14. F. M. Chiussi and A. Francini, "Providing QoS guarantees in packet switches," in Proc. GLOBECOM '99, Rio de Janeireo, Brazil, Dec. 1999, pp. 1582-1590.
15. F. M. Chiussi, A. Francini, D. A. Khotimsky, and S. Krishnan, "Feedback control in a distributed scheduling architecture," in Proc. GLOBECOM 2000, San Francisco, CA, Nov. 2000, pp. 525-531.
16. S. Blake, D. Black, M. Carlson, E. Davies, Z. Wang, and W. Weiss, "An architecture for differentiated services," IETF RFC 2475, Dec. 1998.
17. W. J. Dally and Brian Towles, Principles and Practices of Interconnection Networks. San Francisco, CA: Morgan Kaufman, 2004, pp. 239-249.
18. V. Fineberg, "A practical architecture for implementing end-to-end QoS in an IP network," IEEE Commun. Mag., vol. 40, no. 1, pp. 122-130, Jan. 2002.
19. A. Parekh and R. Gallager, "A generalized processor sharing approach to flow control in integrated services networks: The single-node case," IEEE/ACM Trans. Netw., vol. 1, no. 3, pp. 344-357, Jun. 1993.
20. D. C. Stephens, J. C. R. Bennett, and H. Zhang, "Implementing scheduling algorithms in high-speed networks," IEEE J. Sel. Areas Commun., vol. 17, no. 6, pp. 1145-1158, Jun. 1999.
21. Y. Tamir and G. Frazier, "High performance multiqueue buffers for VLSI communication switches," in Proc. 15th Annu. Symp. Computer Architectures, Honolulu, HI, Jun. 1988, pp. 343-354.
22. N. McKeown, "The iSLIP scheduling algorithm for input-queued switches," IEEE/ACM Trans. Netw., vol. 7, no. 2, pp. 188-201, Apr. 1999.
23. C. Minkenberg, "Performance of i-SLIP scheduling with large roundtrip latency," in Proc. IEEE Workshop on High-Performance Switching and Routing (HPSR 2003), Torino, Italy, Jun. 2003, pp. 49-54.
24. F. M. Chiussi and A. Francini, "A distributed scheduling architecture for scalable packet switches," IEEE J. Sel. Areas Commun., vol. 18, no. 12, pp. 2665-2683, Dec. 2000.
25. S.-T. Chuang, A. Goel, N. McKeown, and B. Prabhakar, "Matching output queueing with a combined input output queued switch," IEEE J. Sel. Areas Commun., vol. 17, no. 6, pp. 1030-1039, Jun. 1999.
26. P. Krishna, N. Patel, A. Charny, and R. J. Simcoe, "On the speedup required for work-conserving crossbar switches," IEEE J. Sel. Areas Commun., vol. 17, no. 6, pp. 1057-1066, Jun. 1999.
27. I. Stoica and H. Zhang, "Exact emulation of an output queueing switch by a combined input output queueing switch," in Proc. 6th Int. Workshop on Quality of Service (IWQoS 98), Napa, CA, 1998, pp. 218-224.
28. C. Minkenberg and T. Engbersen, "A combined input and output queued packet-switched system based on PRIZMA switch-on-a-chip technology," IEEE Commun. Mag., vol. 38, no. 12, pp. 70-77, Dec. 2000.
29. M. Katevenis, D. Serpanos, and E. Spyridakis, "Switching fabrics with internal backpressure using the ATLAS I single-chip ATM switch," in Proc. GLOBECOM '97, Phoenix, AZ, Nov. 1997, pp. 242-246.
30. R. Rojas-Cessa, E. Oki, and H. J. Chao, "CIXOB-k: Combined input-crosspoint-output buffered packet switch," in Proc. GLOBECOM '01, 2001, vol. 4, pp. 2654-2660.
31. D. C. Stephens and H. Zhang, "Implementing distributed packet fair queueing in a scalable switch architecture," in Proc. IEEE INFOCOM '98, San Francisco, CA, 1998, vol. 1, pp. 282-290.
32. M. Nabeshima, "Performance evaluation of a combined input- and crosspoint-queued switch," IEICE Trans. Commun., vol. E83-B, no. 3, pp. 737-74, Mar. 2000.
33. T. Javidi, R. Magill, and T. Hrabik, "A high-throughput scheduling algorithm for a buffered crossbar switch fabric," in Proc. ICC 2001 Helsinki, Finland, Jun. 2001, vol. 5, pp. 1586-1591.
34. H. J. Chao, S. Y. Liew, and Z. Jing, "A dual-level matching algorithm for 3-stage closed-network packet switches," in Proc. Hot Interconnects 2003, Stanford, CA, Aug. 2003, pp. 38-43.
35. F. Abel, C. Minkenberg, R. P. Luijten, M. Gusat, and I. Iliadis, "A four-terabit packet switch supporting long round-trip times," IEEE Micro, vol. 23, pp. 10-24, Jan./Feb. 2003.
36. J. W. Causey and H. S. Kim, "Comparison of buffer allocation schemes in ATM switches: Complete sharing, partial sharing, and dedicated allocation," in Proc. ICC '94, New Orleans, LA, 1994, pp. 1164-1168.
37. F. Le Maut and G. Garcia, "A scalable switch fabric to multi-terabit: Architecture and challenges," in Proc. Hot Chips 2002, 14th Symp. High Performance Chips, Palo Alto, CA, Aug. 2002.
38. N. T. Kung and R. Morris, "Credit-based flow control for ATM networks," IEEE Network, vol. 9, no. 2, pp. 40-48, Mar./Apr. 1995.
39. F. Gramsamer, M. Gusat, and R. Luijten, "Flow control scheduling," J. Microprocess. Microsyst., vol. 27, no. 5-6, pp. 233-241, Jun. 2003.
40. M. Katevenis, "Buffer requirements of credit-based flow control when a minimum draining rate is guaranteed," in Proc. HPCS '97, Chaldiki, Greece, 1997, pp. 168-178.
41. R. P. Luijten, C. Minkenberg, and M. Gusat, "Reducing memory size in buffered crossbars with large internal flow control latency," in Proc. GLOBECOM 2003, San Francisco, CA, Dec. 2003, vol. 7, pp. 3683-3687.
42. S. Floyd and V. Jacobson, "Link-sharing and resource management models for packet networks," IEEE/ACM Trans. Netw., vol. 3, no. 4, pp. 365-386, Aug. 1995.