-
1
-
-
4544359901
-
SOP: What is it and why? A new microsystem-integration technology paradigm-moore's law for system integration of miniaturized convergent systems of the next decade
-
May
-
R. Tummala, "SOP: What is it and why? A new microsystem-integration technology paradigm-moore's law for system integration of miniaturized convergent systems of the next decade," IEEE Trans. Adv. Packag., vol. 27, no. 2, pp. 241-249, May 2004.
-
(2004)
IEEE Trans. Adv. Packag
, vol.27
, Issue.2
, pp. 241-249
-
-
Tummala, R.1
-
2
-
-
4544255367
-
Chip-to-chip optoelectronics SOP on organic boards or packages
-
May
-
G. Chang, D. Guidotti, F. Liu, Y. Chang, Z. Huang, V. Sundaram, D. Balaraman, S. Hegde, and R. Tummala, "Chip-to-chip optoelectronics SOP on organic boards or packages," IEEE Trans. Adv. Packag., vol. 27, no. 2, pp. 386-397, May 2004.
-
(2004)
IEEE Trans. Adv. Packag
, vol.27
, Issue.2
, pp. 386-397
-
-
Chang, G.1
Guidotti, D.2
Liu, F.3
Chang, Y.4
Huang, Z.5
Sundaram, V.6
Balaraman, D.7
Hegde, S.8
Tummala, R.9
-
3
-
-
0026810890
-
Analysis of thermal vias in high density interconnect technology
-
S. Lee, T. Lemczyk, and M. Yovanovich, "Analysis of thermal vias in high density interconnect technology," in Proc. IEEE Semi-Therm Symp., 1992, pp. 55-61.
-
(1992)
Proc. IEEE Semi-Therm Symp
, pp. 55-61
-
-
Lee, S.1
Lemczyk, T.2
Yovanovich, M.3
-
4
-
-
0034452563
-
Effect of via separation and low-k dielectric materials on the thermal characteristics of CU interconnects
-
T. Chiang, K. Banerjee, and K. Saraswat, "Effect of via separation and low-k dielectric materials on the thermal characteristics of CU interconnects," in IEDM Tech. Dig., 2000, pp. 261-264.
-
(2000)
IEDM Tech. Dig
, pp. 261-264
-
-
Chiang, T.1
Banerjee, K.2
Saraswat, K.3
-
5
-
-
84886706699
-
Physical design of optoelectronic system-on-a-package: A CAD tool and algorithms
-
C. Seo, A. Chatterjee, and N. Jokerst, "Physical design of optoelectronic system-on-a-package: A CAD tool and algorithms," in Proc. 6th Int. Symp. Qual. Electron. Design, 2005, pp. 567-572.
-
(2005)
Proc. 6th Int. Symp. Qual. Electron. Design
, pp. 567-572
-
-
Seo, C.1
Chatterjee, A.2
Jokerst, N.3
-
6
-
-
2942658008
-
Design and optimization of board-level optical clock distribution network for high-performance optoelectronic system-on-a-packages
-
C. Seo, A. Chatterjee, S. Cho, and N. Jokerst, "Design and optimization of board-level optical clock distribution network for high-performance optoelectronic system-on-a-packages," in Proc. 14th ACM Great Lakes Symp. VLSI, 2004, pp. 292-297.
-
(2004)
Proc. 14th ACM Great Lakes Symp. VLSI
, pp. 292-297
-
-
Seo, C.1
Chatterjee, A.2
Cho, S.3
Jokerst, N.4
-
7
-
-
0031628846
-
Optimization of thermal via design parameters based on an analytical thermal resistance model
-
R. S. Li, "Optimization of thermal via design parameters based on an analytical thermal resistance model," in 6th Intersoc. Therm. Thermomech. Phenom. Electron. Syst., 1998, pp. 475-580.
-
(1998)
6th Intersoc. Therm. Thermomech. Phenom. Electron. Syst
, pp. 475-580
-
-
Li, R.S.1
-
8
-
-
0034481271
-
Corner block list: An effective and efficient topological representation of non-slicing floorplan
-
X. Hong, G. Huang, Y. Cai, S. Dong, C. K. Cheng, and J. Gu, "Corner block list: An effective and efficient topological representation of non-slicing floorplan," in Proc. IEEE Int. Conf. Computer-Aided Design, 2000, pp. 8-12.
-
(2000)
Proc. IEEE Int. Conf. Computer-Aided Design
, pp. 8-12
-
-
Hong, X.1
Huang, G.2
Cai, Y.3
Dong, S.4
Cheng, C.K.5
Gu, J.6
-
9
-
-
34748823693
-
The transient response of damped linear networks with particular regard to wideband amplifiers
-
W. Elmore, "The transient response of damped linear networks with particular regard to wideband amplifiers," J. Appl. Phys., pp. 55-63, 1948.
-
(1948)
J. Appl. Phys
, pp. 55-63
-
-
Elmore, W.1
-
10
-
-
33748314386
-
Placement and routing for 3-D system-on-package designs
-
Sep
-
J. Minz, E. Wong, M. Pathak, and S. K. Lim, "Placement and routing for 3-D system-on-package designs," IEEE Trans. Compon. Packag. Technol. vol. 29, no. 3, pp. 644-657, Sep. 2005.
-
(2005)
IEEE Trans. Compon. Packag. Technol
, vol.29
, Issue.3
, pp. 644-657
-
-
Minz, J.1
Wong, E.2
Pathak, M.3
Lim, S.K.4
-
11
-
-
0031705566
-
Efficient algorithms for the minimum shortest path steiner arborescence problem with applications to VLSI physical design
-
Jan
-
J. Cong, A. B. Kahng, and K.-S. Leung, "Efficient algorithms for the minimum shortest path steiner arborescence problem with applications to VLSI physical design," IEEE Trans. Computer-Aided Design Intgr. Circuits Syst., vol. 17, no. 1, pp. 24-39, Jan. 1998.
-
(1998)
IEEE Trans. Computer-Aided Design Intgr. Circuits Syst
, vol.17
, Issue.1
, pp. 24-39
-
-
Cong, J.1
Kahng, A.B.2
Leung, K.-S.3
-
13
-
-
0026627087
-
The rectilinear steiner arboresence problem
-
S. K. Rao, P. Sadayappan, F. K. Hwang, and P. W. Shor, "The rectilinear steiner arboresence problem," Algorithmica, pp. 277-288, 1992.
-
(1992)
Algorithmica
, pp. 277-288
-
-
Rao, S.K.1
Sadayappan, P.2
Hwang, F.K.3
Shor, P.W.4
-
14
-
-
0031358448
-
Interconnect design for deep submicron ICs
-
J. Cong, L. He, K. Y. Khoo, C. K. Koh, and Z. Pan, "Interconnect design for deep submicron ICs," in Proc. IEEE Int. Conf. Computer-Aided Design, 1997, pp. 478-485.
-
(1997)
Proc. IEEE Int. Conf. Computer-Aided Design
, pp. 478-485
-
-
Cong, J.1
He, L.2
Khoo, K.Y.3
Koh, C.K.4
Pan, Z.5
|