Design and optimization of board-level optical clock distribution network for high-performance optoelectronic system-on-a-packages

Proceedings of the ACM Great Lakes Symposium on VLSI

Volumn , Issue , 2004, Pages 292-297

  Seo, Chung Seok ^a   Chatterjee, Abhijit ^a   Cho, Sang Yeon ^b   Jokerst, Nan M ^b  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b Duke University   (United States)

Author keywords

Asymmetric structure; Clock distribution; Clock routing; H tree; Optical clock distribution; Optical waveguide loss modeling; Optimization; Optoelectronic system on a package

Indexed keywords

ALGORITHMS; BENDING (DEFORMATION); CLOCKS; COMPUTER AIDED DESIGN; DESIGN; DIFFRACTION GRATINGS; OPTICAL WAVEGUIDES; OPTIMIZATION; SIGNAL PROCESSING; WAVE PROPAGATION;

ASYMMETRIC STRUCTURE; CLOCK DISTRIBUTION; CLOCK ROUTING; H-TREE; OPTICAL CLOCK DISTRIBUTION; OPTICAL WAVEGUIDE LOSS MODELING; OPTOELECTRONUC SYSTEM-ON-A-PACKAGE;

OPTOELECTRONIC DEVICES;

EID: 2942658008     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/988952.989023     Document Type: Conference Paper

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