Layer-by-layer assembled charge-trap memory devices with adjustable electronic properties

Nature Nanotechnology

Volumn 2, Issue 12, 2007, Pages 790-795

  Lee, Jang Sik ^a   Cho, Jinhan ^a   Lee, Chiyoung ^a   Kim, Inpyo ^a   Park, Jeongju ^a   Kim, Yong Mu ^a   Shin, Hyunjung ^a   Lee, Jaegab ^a   Caruso, Frank ^b  

^a Kookmin University   (South Korea)

^b UNIVERSITY OF MELBOURNE   (Australia)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONIC PROPERTIES; FLASH MEMORY; GOLD DEPOSITS; HAFNIUM OXIDES; METAL NANOPARTICLES; MULTILAYER FILMS; MULTILAYERS; NANOMETALS; POLYELECTROLYTES;

CRITICAL VOLTAGES; INSULATING LAYERS; MEMORY PERFORMANCE; NANOPARTICLE LAYERS; NANOPARTICLE MULTILAYERS; POLY(STYRENE SULFONATE); PROGRAMMING SPEED; SILICON SUBSTRATES;

GOLD NANOPARTICLES;

ALLYLAMINE DERIVATIVE; GOLD; HAFNIUM; NANOFILM; NANOMATERIAL; NANOPARTICLE; PLATINUM; POLYALLYLAMINE; POLYELECTROLYTE; POLYSTYRENESULFONIC ACID; SILICON; UNCLASSIFIED DRUG;

ARTICLE; DEVICE; ELECTRIC POTENTIAL; ELECTRICITY; ELECTRON DIFFRACTION; ELECTROSTIMULATION; FILM; INFORMATION PROCESSING; INSULATOR ELEMENT; MEMORY CONSOLIDATION; MEMORY DEVICE; MENTAL PERFORMANCE; PRIORITY JOURNAL; SCANNING ELECTRON MICROSCOPY; SEMICONDUCTOR; VISUAL MEMORY;

EID: 36849001927     PISSN: 17483387     EISSN: 17483395     Source Type: Journal    
DOI: 10.1038/nnano.2007.380     Document Type: Article

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