Design, modeling, and characterization of embedded capacitor networks for core decoupling in the package

IEEE Transactions on Advanced Packaging

Volumn 30, Issue 4, 2007, Pages 809-822

  Muthana, Prathap ^a   Engin, Arif Ege ^a   Swaminathan, Madhavan ^a   Tummala, Rao ^a   Sundaram, Venkatesh ^a   Wiedenman, Boyd ^a   Amey, Daniel ^b   Dietz, Karl H ^b   Banerji, Sounak ^b  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b DUPONT COMPANY   (United States)

Author keywords

Decoupling capacitors; Embedded capacitors; Measurement; Midband frequency; Modeling; Package; Power delivery; Simulation; Simultaneous switching noise; Thick film

Indexed keywords

CAPACITANCE; CAPACITORS; CHARACTERIZATION; COMPUTER SIMULATION; EMBEDDED SYSTEMS; INDUCTANCE; INTEGRATED CIRCUIT LAYOUT; NETWORKS (CIRCUITS); SURFACE MOUNT TECHNOLOGY;

DECOUPLING CAPACITORS; EMBEDDED CAPACITOR; MIDBAND FREQUENCY; SURFACE MOUNT DISCRETE;

ELECTRONICS PACKAGING;

EID: 36348985074     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/TADVP.2007.901548     Document Type: Article

References (27)

1. R. Tummala, Fundamentals of Microsystems Packaging, 1st ed. New York: McGraw Hill, 2001.
2. S. J. Chun, "Methodologies for modeling simultaneous switching noise in multi-layered packages and boards," Ph.D. dissertation, Georgia Inst. Technol., Atlanta, Apr. 2002.
3. L. Smith, R. Anderson, D. Forehand, T. Pelc, and T. Roy, "Power distribution system design methodology and capacitor selection for modern CMOS technology," IEEE Trans. Adv. Packag., vol. 22, no. 3, pp. 284-291, Aug. 1999.
4. B. Garben, G. A. Katopis, and W. D. Becker, "Package and chip design optimization for mid-frequency power distribution decoupling," Electrical Performance Electronic Packag., pp. 245-248, 2002.
5. O. P. Mandhana and J. Zhao, "Comparitive study on the effectiveness of on-chip, on package and PCB decoupling for core noise reduction by using broadband power delivery network models," in Electronic Compon. Technol. Conf., 2005, pp. 732-739.
6. N. Na, T. Budell, C. Chiu, E. Tremble, and I. Wemple, "The Effects of On-Chip and Package Decoupling Capacitors and an Efficient ASIC Decoupling Methodology," in Electronic Compon. Technol. Conf., 2004, pp. 556-567.
7. T. Rahal-Arabi, G. Taylor, M. Ma, J. Jones, and C. Webb, "Design and Validation of the Core and I/O's decoupling of the Pentium3 and Pentium4 Processors," Electrical Performance Electronic Packag., pp. 249-252, 2002.
8. R. Ulrich, "Embedded resistors and capacitors for organic-based SOP," IEEE Trans. Adv. Packag., vol. 27, no. 2, pp. 326-331, May 2004.
9. I. Novak, "Lossy power distribution networks with thin dielectric layers and/or thin conductive layers," IEEE Trans. Adv. Packag., vol. 23, no. 3, pp. 353-360, Aug. 2000.
10. H. Kim, B. K. Sun, and J. Kim, "Suppresion of GHz range power/ ground inductive and simultaneous switching noise using embedded film capacitors in multilayer packages and PCBs," IEEE Microw.Wireless Compon. Lett., vol. 14, no. 2, pp. 71-73, Feb. 2004.
11. K. Y. Chen, W. D. Brown, L. W. Schaper, S. S. Ang, and H. A. Naseem, "A study of high frequency performance of thin film capacitors for electronic packaging," IEEE Trans. Adv. Packag., vol. 23, no. 2, pp. 293-302, May 2000.
12. J. S. Peiffer and W. Balliette, "Decoupling of high speed digital electronics with embedded capacitance," presented at the 38th Int. Symp. Microelectron., Philadelphia, PA, Sep. 2005.
13. J. G. Nickel, "Decoupling capacitance platform for substrates, sockets and interposers," presented at the DesignCon, Santa Clara, CA, Feb. 2005.
14. P. Muthana, M. Swaminathan, R. Tummala, V. Sundaram, L. Wan, S. K. Bhattacharya, and P. M. Raj, "Packaging of multi-core processors: Tradeoffs and potential solutions," in Electron. Compon. Technol. Conf., 2005, pp. 1895-1903.
15. H. P. Hofstee, "Future microprocessors and off-chip SOP interconnect," IEEE Trans. Adv. Packag., vol. 27, no. 2, pp. 301-303, May 2004.
16. International Roadmap for Semiconductors (ITRS)_2004 Update, [Online]. Available: http://public.itrs.net
17. J. Felten, R. Snogren, and J. Zhou, "Embedded ceramic resistors and capacitors in PWB: Process and performance," in Fall IPC Meeting, Orlando, FL, Oct. 11, 2001.
18. W. Borland and J. Felten, "Thick film capacitors and resistors inside printed circuit boards," presented at the 34th Int. Symp. Microelectron., Baltimore, MD, Oct. 9-11, 2001.
19. W. Borland, "Designing for embedded passives," Printed Circuit Board Design, Aug. 2001.
20. M. Kamon, M. J. Ttsuk, and J. K. White, "FASTHENRY: A mutipole-accelerated 3D-inductance extraction program," IEEE Trans. Microwave Theory Tech., vol. 42, no. 9, pp. 1750-1758, Sep. 1994.
21. Interra embedded passive materials. DuPont [Online]. Available: www.interra.dupont.com
22. I. Novak and J. R. Miller, "Frequency dependent characterization of bulk and ceramic bypass capacitors," in Poster Material 12th Topical Meeting Electrical Performance Electronic Packag., Oct. 2003, pp. 101-104.
23. J. H. Kim and M. Swaminathan, "Modeling of irregular shaped power distribution planes using transmission matrix method," IEEE Trans. Adv. Packag., vol. 24, no. 3, pp. 334-346, Aug. 2001.
24. J. Choi, S.-H. Min, J.-H. Kim, M. Swaminathan, W. Beyene, and X. Yuan, "Modeling and analysis of power distribution networks for gigabit applications," IEEE Trans. Mobile Comput., vol. 2, no. 4, pp. 299-313, Dec. 2003.
25. W. Beyene, C. Yuan, J. H. Kim, and M. Swaminathan, "Modeling and analysis of power distribution networks for gigabit applications," in Proc. 4th Int. Symp. Quality Electronic Design (ISQED), 2003, pp. 235-240.
26. P. Muthana, M. Swaminathan, R. Tummala, P. M. Raj, E. Engin, L. Wan, D. Balaraman, and S. Bhattacharya, "Design, modeling and characterization of embedded capacitors for mid-frequency decoupling in semiconductor systems," Electromagn. Compatibil., pp. 638-643, 2005.
27. AVX. AVX Corp., Myrtle Beach, SC [Online]. Available: https:// www.avx.com/