Effects of width scaling and layout variation on dual damascene copper interconnect electromigration

Microelectronics Reliability

Volumn 47, Issue 12, 2007, Pages 2100-2108

  Lin, M H ^a,b   Chang, K P ^b   Su, K C ^b   Wang, Tahui ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b UNITED MICROELECTRONICS CORPORATION   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

COPPER; ELECTROMIGRATION; GRAIN BOUNDARIES; INTEGRATED CIRCUIT LAYOUT; POLYCRYSTALLINE MATERIALS; SURFACE DIFFUSION;

DAMASCENE; LAYOUT VARIATION; SURFACE TRANSPORT; WIDTH SCALING;

OPTICAL INTERCONNECTS;

EID: 35649017664     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2006.10.004     Document Type: Article

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