-
1
-
-
0023563047
-
New ultra high density EPROM and flash EEPROM with NAND structure cell
-
F. Masuoka et al., "New Ultra High Density EPROM and Flash EEPROM with NAND Structure Cell," IEEE IEDM Tech. Dig. Papers, (1987) p. 552.
-
(1987)
IEEE IEDM Tech. Dig. Papers
, pp. 552
-
-
Masuoka, F.1
-
2
-
-
33747184810
-
2 contactless memory cell technology for 3V only 64 Mbt EEPROM
-
2 Contactless Memory Cell Technology for 3V only 64 Mbt EEPROM," IEEE IEDM Tech. Dig. Papers, (1992) p. 991.
-
(1992)
IEEE IEDM Tech. Dig. Papers
, pp. 991
-
-
Kume, H.1
-
3
-
-
0003120872
-
A 256 Mb multilevel flash memory with 2 MB/s program rate for mass storage application
-
A. Nozoe et al., "A 256 Mb Multilevel Flash Memory with 2 MB/s Program Rate for Mass Storage Application," IEEE Dig. Tech. Papers ISSCC (1999) p. 110.
-
(1999)
IEEE Dig. Tech. Papers ISSCC
, pp. 110
-
-
Nozoe, A.1
-
4
-
-
0035714776
-
A giga-scale assist-gate (AG)- AND-type flash memory cell with 20-MB/s programming throughput for content-downloading application
-
T. Kobayashi et al., "A Giga-Scale Assist-Gate (AG)- AND-Type Flash Memory Cell with 20-MB/s Programming Throughput for Content-Downloading Application," IEEE IEDM Tech. Dig. Papers, (2001) p. 29.
-
(2001)
IEEE IEDM Tech. Dig. Papers
, pp. 29
-
-
Kobayashi, T.1
-
5
-
-
0242611608
-
Constant-charge-injection programming for 10-MB/s multilevel AG-AND flash memories
-
H. Kurata et al., "Constant-Charge-Injection Programming for 10-MB/s Multilevel AG-AND Flash Memories," Symp. VLSI Circuit. Dig. Tech. Papers, (2001) p. 302.
-
(2001)
Symp. VLSI Circuit. Dig. Tech. Papers
, pp. 302
-
-
Kurata, H.1
-
6
-
-
0036927889
-
10-MB/s multi-level programming of Gb-scale flash memory enabled by new AG-AND cell technology
-
Y. Sasago et al., "10-MB/s Multi-Level Programming of Gb-Scale Flash Memory Enabled by New AG-AND Cell Technology," IEEE IEDM Tech. Dig. Papers, (2002) p. 952.
-
(2002)
IEEE IEDM Tech. Dig. Papers
, pp. 952
-
-
Sasago, Y.1
-
7
-
-
0038306347
-
A 1Gb multilevel AG-AND-type flash memory with 10MB/s programming throughput for mass storage application
-
K. Yoshida et al., "A 1Gb Multilevel AG-AND-Type Flash Memory with 10MB/s Programming Throughput for Mass Storage Application," IEEE Dig. Tech. Papers, ISSCC (2003) p. 288.
-
(2003)
IEEE Dig. Tech. Papers, ISSCC
, pp. 288
-
-
Yoshida, K.1
-
8
-
-
0038306352
-
A 1.8V 2Gb NAND flash memory for mass storage application
-
J. Lee et al., "A 1.8V 2Gb NAND Flash Memory for Mass Storage Application," IEEE Dig. Tech. Papers ISSCC (2003) p. 290.
-
(2003)
IEEE Dig. Tech. Papers ISSCC
, pp. 290
-
-
Lee, J.1
-
9
-
-
0036107954
-
2 1Gb NAND flash memory with 10MB/s programming throughput
-
2 1Gb NAND Flash Memory with 10MB/s Programming Throughput," IEEE Dig. Tech. Papers ISSCC (2002) p. 106.
-
(2002)
IEEE Dig. Tech. Papers ISSCC
, pp. 106
-
-
Nakamura, H.1
-
10
-
-
0020243170
-
EPROM cell with high gate injection efficiency
-
M. Kamiya et al., "EPROM Cell with High Gate Injection Efficiency," IEEE Tech. Dig. IEDM (1982) p. 741.
-
(1982)
IEEE Tech. Dig. IEDM
, pp. 741
-
-
Kamiya, M.1
-
11
-
-
0036575326
-
Effects of floating-gate interference on NAND flash memory cell operation
-
J-D. Lee et al., "Effects of Floating-Gate Interference on NAND Flash Memory Cell Operation," IEEE Electron Device Lett. 23, (2002) p.264.
-
(2002)
IEEE Electron Device Lett.
, vol.23
, pp. 264
-
-
Lee, J.-D.1
-
12
-
-
0033360385
-
Detailed observation of small leak cuirent in flash memories with thin tunnel oxides
-
Y. Manabe et al., "Detailed Observation of Small Leak Cuirent in Flash Memories with Thin Tunnel Oxides," IEEE Trans. Semiconductor Manufacturing, 12 (1999) p. 170.
-
(1999)
IEEE Trans. Semiconductor Manufacturing
, vol.12
, pp. 170
-
-
Manabe, Y.1
-
13
-
-
0032257713
-
Monte Carlo simulation of stress-induced leakage current by hopping conduction via multi-traps in oxide
-
Y. Okuyama et al., "Monte Carlo Simulation of Stress-Induced Leakage Current by Hopping Conduction via Multi-Traps in Oxide," IEEE IEDM Tech. Dig. Papers, (1998) p. 905.
-
(1998)
IEEE IEDM Tech. Dig. Papers
, pp. 905
-
-
Okuyama, Y.1
-
14
-
-
0008986679
-
Anomalous leakage current model for retention failure in flash memories
-
Y. Okuyama et al., "Anomalous Leakage Current Model for Retention Failure in Flash Memories," Ext. Abs. SSDM (1999) p. 530.
-
(1999)
Ext. Abs. SSDM
, pp. 530
-
-
Okuyama, Y.1
-
15
-
-
0028755689
-
Read disturb degradation mechanism due to electron trapping in the tunnel oxide for low-voltage flash memories
-
M. Kato et al., "Read Disturb Degradation Mechanism due to Electron Trapping in the Tunnel Oxide for Low-Voltage Flash memories," IEEE IEDM Tech. Dig. Papers, (1994) p. 45.
-
(1994)
IEEE IEDM Tech. Dig. Papers
, pp. 45
-
-
Kato, M.1
-
16
-
-
0034784950
-
A novel analysis method of threshold voltage shift due to detrap in a multi-level flash memory
-
R. Yamada et al., "A Novel Analysis Method of Threshold Voltage Shift due to Detrap in a Multi-level Flash Memory," Symp. VLSI Tech. Dig. Tech. Papers, (2001) p. 115.
-
(2001)
Symp. VLSI Tech. Dig. Tech. Papers
, pp. 115
-
-
Yamada, R.1
-
17
-
-
0029723449
-
20-Mb/s erase/record flash memory by asymmetrical operation
-
T. Kawabara et al., "20-Mb/s Erase/Record Flash Memory by Asymmetrical Operation," Symp. of VLSI Circuits Dig. Tech. Papers, (1996) p. 174.
-
(1996)
Symp. of VLSI Circuits Dig. Tech. Papers
, pp. 174
-
-
Kawabara, T.1
-
18
-
-
0033701274
-
A dual page programming scheme for high-speed multi-Gb-scale flash memories
-
K. Takeuchi et al., "A Dual Page Programming Scheme for High-Speed Multi-Gb-Scale Flash Memories," Symp. of VLSI Circuits Dig. Tech. Papers, (2000) p. 156.
-
(2000)
Symp. of VLSI Circuits Dig. Tech. Papers
, pp. 156
-
-
Takeuchi, K.1
-
19
-
-
84946412792
-
-
Feb. (in Japanese)
-
S. Lai, NIKKEI MICRODEVICES (Feb. 1997) p.62 (in Japanese).
-
(1997)
Nikkei Microdevices
, pp. 62
-
-
Lai, S.1
-
20
-
-
0034315780
-
NROM: A novel localized trapping, 2-bit nonvolatile memory cell
-
B. Eitan et al., "NROM: A novel localized trapping, 2-bit nonvolatile memory cell," IEEE Trans Electron Devices Lett. 21 (2000) p.543.
-
(2000)
IEEE Trans Electron Devices Lett.
, vol.21
, pp. 543
-
-
Eitan, B.1
-
21
-
-
0035716099
-
Novel ultra high density flash memory with a stacked-surrounding gate transistor (S-SGT) structure cell
-
T. Endo et al., "Novel Ultra High Density Flash Memory with a Stacked-Surrounding Gate Transistor (S-SGT) Structure Cell," IEEE IEDM Tech. Dig. Papers, (2001) p. 33.
-
(2001)
IEEE IEDM Tech. Dig. Papers
, pp. 33
-
-
Endo, T.1
|