Novel ultra high density flash memory with a stacked-surrounding gate transistor (S-SGT) structured cell

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2001, Pages 33-36

  Endoh, Tetsuo ^a   Kinoshita, Kazushi ^b   Tanigami, Takuji ^a   Wada, Yoshihisa ^b   Sato, Kota ^b   Yamada, Kazuya ^b   Yokoyama, Takashi ^a   Takeuchi, Noburo ^a   Tanaka, Kenichi ^b   Awaya, Nobuyoshi ^b   Sakiyama, Keizou ^b   Masuoka, Fujio ^a  

^a TOHOKU UNIVERSITY   (Japan)

^b SHARP CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRON TUNNELING; ETCHING; LOGIC DESIGN; LOGIC GATES; NAND CIRCUITS; SCANNING ELECTRON MICROSCOPY; SILICON; SUBSTRATES; THRESHOLD VOLTAGE; TRANSISTORS;

FOWLER-NORDHEIM TUNNELING ELECTRON; NAND FLASH MEMORY CELL; SILICON PILLAR; STACKED-SURROUNDING GATE TRANSISTOR; ULTRA HIGH DENSITY FLASH MEMORY; VERTICAL SELF-ALLIGNED PROCESS;

FLASH MEMORY;

EID: 0035716099     PISSN: 01631918     EISSN: None     Source Type: Journal    
DOI: 10.1109/IEDM.2001.979396     Document Type: Article

References (3)

1. New ultra high density eprom and flash eeprom with NAND structure cell
2. A novel surface-oxidized barrier-SiN cell technology to improve endurance and read-disturb characteristics for gigabit NAND flash memories technical digest
3. Floating channel type SGT flash memory