A novel analysis method of threshold voltage shift due to detrap in a multi-level flash memory

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue TECHNOLOGY SYMP., 2001, Pages 115-116

  Yamada, R I ^a   Sekiguchi, T ^a   Okuyama, Y ^a   Yugami, J ^a   Kume, H ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DEGRADATION; ELECTRON TRAPS; ELECTRON TUNNELING; HOLE TRAPS; THRESHOLD VOLTAGE;

MULTI-LEVEL FLASH MEMORY;

FLASH MEMORY;

EID: 0034784950     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)