An overview of a compiler for mapping software binaries to hardware

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 15, Issue 11, 2007, Pages 1177-1190

  Mittal, Gaurav ^b,c   Zaretsky, David ^b,c   Tang, Xiaoyong ^a,d   Banerjee, Prith ^a,b  

^a IEEE

^b University of Illinois at Chicago   (United States)

^c Binachip Inc   (United States)

^d MAGMA DESIGN AUTOMATION   (United States)

Author keywords

Binary translation; Compiler; Decompilation; Hardware software codesign; High level synthesis; Reconfigurable computing

Indexed keywords

CONFORMAL MAPPING; DIGITAL SIGNAL PROCESSING; EMBEDDED SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); PROGRAM COMPILERS; SOFTWARE ENGINEERING;

BINARY TRANSLATION; HARDWARE-SOFTWARE CODESIGN; HIGH-LEVEL SYNTHESIS; RECONFIGURABLE COMPUTING;

BINARY CODES;

EID: 35448934818     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2007.904095     Document Type: Review

References (53)

1. G. De Micheli, Synthesis and Optimization o}Digital Circuits. New York: McGraw Hill, 1994.
2. S. S. Muchnick, Advanced Compiler Design Implementation. San Mateo, CA: Morgan Kaufmann, 1997.
3. Synplicity Corporation, Sunnyvale, CA, "Synplify Pro Datasheet," 2005. [Online]. Available: www.synplicity.com
4. "TMS320C6000 Architecture Description," Texas Instruments, Dallas, CA, 2006. [Online]. Available: www.ti.com
5. N. Ramsey and M. F. Fernandez, "Specifying representations of machine instructions," ACM Trans. Program. Lang. Syst., vol. 19, no. 3, pp. 492-524, May 1997.
6. N. Ramsey and M. F. Fernandez, "New Jersey machine-code toolkit," in Proc. USENIX Tech. Conf., 1995, pp. 289-302.
7. C. Cifuentes and K. J. Gough, "A methodology for decomposition," in Proc. XIX Conf. Latinoamer. Inf., 1993, pp. 257-266.
8. C. Cifuentas and V. Malhotra, "Binary translation: Static, dynamic, retargetable?," in Proc. Int. Conf. Softw. Maint., 1996, pp. 340-349.
9. A. Klaiber, "The technology behind crusoe processors," Transmeta Corp., Santa Clara, CA, 2000. [Online]. Available: www.transmeta.com
10. A. Jones et al., "PACT HDL: A C compiler with power and performance optimizations," in Proc. CASES, 2002, pp. 188-197.
11. G. Stitt and F. Vahid, "Hardware/software partitioning of software binaries," in Proc. Int. Conf. Comput.-Aided Des. (ICCAD), 2002, pp. 164-170.
12. G. Stitt et al., "Dynamic hardware/software partitioning: A first approach," in Proc. Des. Autom. Conf., 2003, pp. 250-255.
13. B. Levine and H. Schmit, "Efficient application representation for HASTE: Hybrid architectures with a single executable," in Proc. IEEE Symp. FCCM, 2003, p. 101.
14. Z. Ye et al., "CHIMAERA: A high-performance architecture with a tightly-coupled reconfigurable functional unit," in Proc. 27th Int. Symp. Comput. Arch., 2000, pp. 225-235.
15. "Cascade tool set," CriticalBlue, Edinburgh, U.K., 2005. [Online]. Available: www.criticalblue.com.
16. V. Bala et al., "Dynamo: A transparent dynamic optimization system," in Proc. ACM SIGPLAN Conf. Program. Lang. Des. Implement. (PLDI), 2000, pp. 1-12.
17. M. Gschwind et al., "Dynamic and transparent binary translation," IEEE Comput. Mag., vol. 33, no. 3, pp. 54-59, Mar. 2000.
18. D. Callahan et al., "Constructing the procedure call multigraph," IEEE Trans. Softw. Eng., vol. 16, no. 4, pp. 483-487, Apr. 1990.
19. Xilinx, Inc., San Jose, CA, "Xilinx Virtex II datasheets," 2005. [Online]. Available: www.xilinx.com
20. K. Cooper et al., "Building a control-flow graph from scheduled assembly code," Dept. Comput. Sci., Rice Univ., Houston, TX, Tech. Rep. TR02-399, 2002.
21. M. Bailey and J. Davidson, "A formal model and specification language for procedure calling conventions," in Proc. ACM Symp. Principles Program. Lang., 1995, pp. 298-310.
22. M. J. Van Emmerik, "Identifying library functions in executable files using patterns," in Proc. Australian Softw. Eng. Conf., 1998, p. 90.
23. C. Cifuentes and D. Simon, "Procedure abstraction recovery from, binary code," in Proc. 4th Eur. Conf. Softw. Maint. Reeng., 2000, p. 55.
24. ARM Inc., Austin, TX, "ARM7 processor family," 2005. [Online]. Available: www.arm.com/products/CPUs/families/ARM7Family.html
25. ARM Inc., Austin, TX, "ARM9 processor family," 2005. [Online]. Available: www.arm.com/products/CPUs/families/ARM9Family.html
26. Intel Corp., Santa Clara, CA, "Intel StrongARM SA 1100 microprocessor developers manual," 2001.
27. MIPS Technologies Inc., Mountain View, CA, "MIPS R3000 datasheet," 1997. [Online]. Available: www.mips.com
28. Texas Instruments, Dallas, TX, "TMS320 C6000 Architecture Description." 2004. [Online]. Available: www.ti.com.
29. Mathworks, Inc., Natick, MA, "Real-time workshop datasheet," 2004. [Online]. Available: www.mathworks.com
30. G. Mittel, D. Zaretsky, G. Memik, and P. Banerjee, "Automatic extraction of function bodies from software binaries," in Proc. IEEE/ACM Asia South Pac. Des. Autom. Conf. (ASPDAC), 2005, pp. 928-931.
31. D. Zaretsky, G. Mittal, R. Dick, and P. Banerjee, "Generation of control and data flow graphs from scheduled and pipelined assembly code," in Proc. LCPC, 2006, pp. 76-90.
32. D. Zaretsky, "A methodology for translating scheduled software binaries onto field programmable gate arrays," Ph.D. dissertation, Electr. Comput. Eng. Dept., Northwestern Univ., Evanston, IL, 2005.
33. G. Mittal, "A compiler infrastructure for compiling assembly and binary programs onto FPGAS," Ph.D. dissertation, Elect. Comput. Eng. Dep., Northwestern Univ., Evanston, IL, 2004.
34. M. S. Hecht, Flow Analysis of Computer Pmgrams. New York: Elsevier Sci. Inc., 1977.
35. D. Zaretsky, G. Mittal, R. Dick, and P. Banerjee, "Balanced scheduling and operation chaining in high-level synthesis for FPGA designs," in Proc. 12th Asia South Pac. Des. Autom. Conf., 2007, pp. 595-601.
36. T. Jiang, X. Tang, and P. Banerjee, "Macro-models for high level area and power estimation on FPGAs," in Proc. 14th ACM Great Lakes Symp. VLSI, 2004, pp. 162-165.
37. C. Fleming, "A tutorial on convolutional coding with viterbi decoding," 2005. [Online]. Available: http://home.netcom.com/~chip.f/ viterbi/tutorial.html
38. C. Lee, M. Potkonjak, and W. H. Mangione-Smith, "MediaBench: A tool for evaluating and synthesizing multimedia and communications systems," in Proc. Int. Symp. Microarch., 1997, pp. 330-335.
39. J. Huck, D. Morris, J. Ross, A. Knies, H. Mulder, and R. Zahir, "Introducing the IA-64 architecture," IEEE Micro, vol. 20, no. 5, pp. 12-23, Sep./Oct. 2000.
40. Altera, San Jose, CA, "Stratix datasheet," 2005. [Online]. Available: www.altera.com.
41. P. Paulin and J. Knight, "Force-Directed scheduling for the behavioral synthesis of ASICs," IEEE Trans. Comput.-Aided Des., vol. 8, no. 6, pp. 661-679, Jun. 1989.
42. D. Zaretsky, G. Mittal, R. Dick, and P. Banerjee, "Dynamic template generation for resource sharing in control and data flow graphs," in Proc. Int. Conf. VLSI Des., 2006, pp. 465-468.
43. G. Stitt, Z. Guo, F. Vahid, and W. Najjar, "Techniques for synthesizing binaries to an advanced register/memory structure," in Proc. ACM/SIGDA Symp. Field Program. Gate Arrays (FPGA), 2005, pp. 118-124.
44. G. Mittal, D. Zaretsky, X. Tang, and P. Banerjee, "Automatic translation of software binaries onto FPGAs," in Proc. Des. Autom. Conf. (DAC), 2004, pp. 389-394.
45. Tensilica Inc., Santa Clara, CA, "XPRES compiler," 2005. [Online]. Available: http://www.tensilica.com/products/xpres.htm
46. M. Fernandez and R. Espasa, "Dixie: A retargetable binary instrumentation tool," in Proc. X J. Paral., Manga Mar Menor, Murcia, 1999, pp. 143-148.
47. J. J. Dongarra and A. R. Hinds, "Unrolling loops in FORTRAN," Softw. -Practice Experience, vol. 9, pp. 219-226, 1979.
48. J. W. Davidson and S. Jinturkar, "An aggressive approach to loop unrolling," Dept. Comput. Sci., Univ. Virginia, Charlottesville, Tech. Rep. CS-95-26, 1995.
49. M. Budiu and S. C. Goldstein, "Pegasus: An efficient intermediate representation," Carnegie Mellon Univ., Pittsburgh, PA, Tech. Rep. CMU-CS-02-107, 2002,
50. A. Settle, I. Bratt, and D. Connors, "Predicate-based transformations to eliminate control and data-irrelevant cache misses," in Proc. 1st Workshop Explicitly Paral. Inst. Comput. Arch. Compilers, 2001, pp. 15-22.
51. C.-T. Hwang, J.-H. Lee, and Y.-C. Hsu, "A formal approach to the scheduling problem in high-level synthesis," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 10, no. 4, pp. 464-474, Apr. 1991.
52. G. Stitt and F. Vahid, "New decompilation techniques for binary-level co-processor generation," in Proc. IEEE/ACM Int. Conf. Comput.-Aided Des., 2005, pp. 547-554.
53. C. Cifuentes, "Reverse compilation techniques," Ph.D. dissertation, Faculty Inf. Technol., Queensland Univ. Technol., Brisbane, Australia, 1994.