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Volumn , Issue , 2002, Pages 188-197
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PACT HDL: A C compiler targeting ASICs and FPGAs with power and performance optimizations
a
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Author keywords
ASIC; Compiler; FPGA; FSM; HDL; High performance; IP; Levelization; Low power; Pipelining; SoC; Synthesis; Verilog; VHDL
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Indexed keywords
APPLICATION-SPECIFIC HARDWARE;
ASIC;
C COMPILERS;
CHIP FABRICATION TECHNOLOGY;
COMMERCIAL TOOLS;
COMPILATION PROCESS;
COMPLEX ALGORITHMS;
CUSTOM HARDWARES;
DESIGN TIME;
HARDWARE ARCHITECTURE;
HARDWARE DESCRIPTIONS;
HARDWARE DESIGN;
HARDWARE DESIGNERS;
HARDWARE SYNTHESIS;
HIGH LEVEL ALGORITHMS;
INDUSTRY STANDARDS;
LOGIC DENSITY;
LOW POWER;
PERFORMANCE OPTIMIZATIONS;
POWER DISSIPATION;
REPROGRAMMABLE;
SUBMICRON;
SYSTEM ON A CHIP;
VERILOG;
VERILOG VHDL;
COMPUTER HARDWARE;
DESIGN;
ELECTRIC POWER SUPPLIES TO APPARATUS;
EMBEDDED SYSTEMS;
HARDWARE;
HIGH LEVEL LANGUAGES;
PROGRAM COMPILERS;
PROGRAMMABLE LOGIC CONTROLLERS;
SIGNAL PROCESSING;
SYNTHESIS (CHEMICAL);
COMPUTER HARDWARE DESCRIPTION LANGUAGES;
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EID: 35248864303
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1145/581630.581659 Document Type: Conference Paper |
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Times cited : (11)
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References (39)
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