Balanced scheduling and operation chaining in high-level synthesis for FPGA designs

Proceedings - Eighth International Symposium on Quality Electronic Design, ISQED 2007

Volumn , Issue , 2007, Pages 595-601

  Zaretsky, David C ^a   Mittal, Gaurav ^a   Dick, Robert P ^b   Banerjee, Prith ^a  

^a University of Illinois at Chicago

^b Northwestern University

Author keywords

[No Author keywords available]

Indexed keywords

APPROXIMATION THEORY; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); PARAMETER ESTIMATION; PROBLEM SOLVING; ROUTING ALGORITHMS;

CHAINING ROUTINE; CRITICAL TIMING PATHS; OPERATION CHAINING; OPTIMAL PERFORMANCE REMAIN CHALLENGING PROBLEMS;

SCHEDULING;

EID: 34548124895     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2007.41     Document Type: Conference Paper

References (16)

1. G. De Micheli, Synthesis and Optimization of Digital Circuits. McGraw Hill, 1994.
2. P. Paulin and J. Knight, "Force-Directed Scheduling for the Behavioral Synthesis of ASICs," in IEEE Transactions on Computer-Aided Design, vol. 8, no. 6, June 1989.
3. P. Paulin and J. Knight, "Scheduling and Binding Algorithms for High-Level Synthesis," in Proceedings of the Design and Automation Conference, Las Vegas, NV, June 1989.
4. W. Verhaegh, P. Lippens, E. Aarts, J. Korst, A. Werf, and J. Meerbergen, "Efficiency Improvements for Force-Directed Scheduling," in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, Nov. 1992.
5. D. Kerns and S. Eggers, "Balanced Scheduling: Instruction Scheduling when Memory Latency is Uncertain," in ACM SIGPLAN Notices, vol. 39, issue 4, Apr. 2004.
6. G. Mittal, D. Zaretsky, X. Tang, and P. Banerjee, "Automatic Translation of Software Binaries onto FPGAs," in Proceedings of the 41 st Annual Conference on Design Automation, 2004.
7. D. Zaretsky, G. Mittal, X. Tang, and P. Banerjee, "Overview of the FREEDOM Compiler for Mapping DSP Software to FPGAs," in Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, CA, 2004.
8. A. Srinivasan, G. Huber, and D. LaPotin, "Accurate Area and Delay Estimations from RTL Descriptions," in IEEE Transactions on VLSI Systems, vol. 6, no. 1, March 1998.
9. M. Nemani and F. Najm, "Delay Estimation of VLSI Circuits from a High-Level View," in Proceedings of the 35th Annual Design Automation Conference, San Francisco, CA, 1998.
10. M. Nourani and C. Papachristou, "False Path Exclusion in Delay Analysis of RTL-Based Datapath-Controller Designs," in Proceedings of the Conference on European Design Automation, Geneva, Switzerland, Sept. 1996.
11. M. Xu and F. Kurdahi, "Area and Timing Estimation for Lookup Table Based FPGAs," in Proceedings of the 1996 European Conference on Design and Test, Mar. 1996.
12. A. Nayak, M. Haldar, A. Choudhary, and P. Banerjee, "Accurate Area and Delay Estimators for FPGAs," in Proceedings of the Conference on Design, Automation and Test in Europe, Mar. 2002.
13. T. Jiang, X. Tang, and P. Banerjee, "Macro-models for high level area and power estimation on FPGAs," in Proceedings of the 14th ACM Great Lakes symposium on VLSI, Boston, MA, Apr. 2004.
14. C. E. Leiserson and J. B. Saxe, "Retiming Synchronous Circuitry," in Algorithmica, Vol. 6, No. 1, 1991.
15. S. Malik, E. Sentovich, R. Brayton, and A. Sangiovanni-Vincentelli, "Retiming and Resynthesis: Optimization of Sequential Networks with Combinational Techniques," in IEEE Transactions on Computer-Aided Design of Integrated Circuits, Jan. 1991.
16. H. Zhou, V. Singhal, and A. Aziz, "How Powerful is Retiming?" in Proceedings of the IEEE/ACM International Workshop on Logic Synthesis, May 1998.