Automatic application-specific instruction-set extensions under microarchitectural constraints

International Journal of Parallel Programming

Volumn 31, Issue 6, 2003, Pages 411-428

  Atasu, Kubilay ^a   Pozzi, Laura ^b   Lenne, Paolo ^b  

^a BOGAZICI UNIVERSITY   (Turkey)

^b EPFL   (Switzerland)

Author keywords

Automatic partitioning; Customisable processors; Hardware software codesign; Instruction set extensions

Indexed keywords

ALGORITHMS; CONSTRAINT THEORY; DATA STORAGE EQUIPMENT; EMBEDDED SYSTEMS; GRAPH THEORY; HEURISTIC METHODS; MATHEMATICAL MODELS; OPTIMIZATION; PROGRAM PROCESSORS; SOFTWARE ENGINEERING;

AUTOMATIC PARTITIONING; CUSTOMIZABLE PROCESSORS; HARDWARE/SOFTWARE CODESIGN; INSTRUCTION-SET EXTENSIONS;

PARALLEL PROCESSING SYSTEMS;

EID: 3543091438     PISSN: 08857458     EISSN: None     Source Type: Journal    
DOI: 10.1023/B:IJPP.0000004508.14594.b9     Document Type: Conference Paper

References (18)

1. B. K. Holmer, Automatic Design of Computer Instruction Sets, Ph.D. thesis, University of California, Berkeley, California (1993).
2. J. Van Praet, G. Goossens, D. Lanneer, and H. De Man, Instruction Set Definition and Instruction Selection for ASIPs, Proceedings of the 7th International Symposium on High-Level Synthesis, Niagara-on-the-Lake, Ontario, pp. 11-16 (April 1994).
3. I.-J. Huang and A. M. Despain, Synthesis of Application Specific Instruction Sets, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems CAD, 14(6):663-675 (June 1995).
4. F. Campi, R. Canegallo, and R. Guerrieri, IP-Reusable 32-Bit VLIW Risc Core, Proceedings of the European Solid State Circuits Conference, Villach, Austria, pp. 456-459 (September 2001).
5. T. R. Halfhill, MIPS Embraces Configurable Technology, Microprocessor Report, (3rd March 2003).
6. A. Wang, E. Killian, D. Maydan, and C. Rowen, Hardware/Software Instruction Set Configurability for System-on-Chip Processors, Proceedings of the 38th Design Automation Conference, Las Vegas, Nevada, pp. 184-188 (June 2001).
7. T. R. Halfhill, ARC Cores Encourages "Plug-Ins," Microprocessor Report (19th June 2000).
8. P. Faraboschi, G. Brown, J. A. Fisher, G. Desoli, and F. Homewood, Lx: A Technology Platform for Customizable VLIW Embedded Processing, Proceedings of the 27th Annual International Symposium on Computer Architecture, Vancouver, pp. 203-213 (June 2000).
9. H. Choi, J.-S. Kim, C.-W. Yoon, I.-C. Park, S. H. Hwang, and C.-M. Kyung, Synthesis of Application Specific Instructions for Embedded DSP Software, IEEE Transactions on Computers C, 48(6):603-614 (June 1999).
10. R. Kastner, A. Kaplan, S. O. Memik, and E. Bozorgzadeh, Instruction Generation for Hybrid Reconfigurable Systems, A CM Transactions on Design Automation of Embedded Systems (TODAES), 7(4):605-627 (October 2002).
11. M. Arnold and H. Corporaal, Designing Domain Specific Processors, Proceedings of the 9th International Workshop on Hardware/Software Codesign, Copenhagen, pp. 61-66 (April 2001).
12. R. Razdan and M. D. Smith, A High-Performance Microarchitecture with Hardware-Programmable Functional Units, Proceedings of the 27th International Symposium on Microarchitecture, San Jose, California, pp. 172-180 (November 1994).
13. C. Alippi, W. Fornaciari, L. Pozzi, and M. Sami, A DAG Based Design Approach for Reconfigurable VLIW Processors, Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, pp. 778-779 (March 1999).
14. B. Kastrup, A. Bink, and J. Hoogerbrugge, ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accelerator, Proceedings of the 5th IEEE Symposium on Field-Programmable Custom Computing Machines, Napa Valley, California (April 1999).
15. Z. A. Ye, A. Moshovos, S. Hauck, and P. Banerjee, CHIMAERA: A High-Performance Architecture with a Tightly-Coupled Reconfigurable Functional Unit, Proceedings of the 27th Annual International Symposium on Computer Architecture, Vancouver, pp. 225-235 (June 2000).
16. M. Baleani, F. Gennari, Y. Jiang, Y. Patel, R. K. Brayton, and A. Sangiovanni-Vincentelli, HW/SW Partitioning and Code Generation of Embedded Control Applications on a Reconfigurable Architecture Platform, Proceedings of the 10th International Workshop on Hardware/Software Codesign, Estes Park, Colorado, pp. 151-156 (May 2002).
17. C. Lee, M. Potkonjak, and W. H. Mangione-Smith, MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems, Proceedings of the 30th Annual International Symposium on Microarchitecture, Research Triangle Park, North Carolina, pp. 330-335 (December 1997).
18. M. D. Smith and G. Holloway, An Introduction to Machine SUIF and its Portable Libraries for Analysis and Optimization, Harvard University, Cambridge, Massachusetts (2000). http://www.eecs.harvard.edu/hube/software/.