IP-reusable 32-bit VLIW risc core

European Solid-State Circuits Conference

Volumn , Issue , 2001, Pages 445-448

  Campi, F ^a   Canegallo, R ^b   Guerrieri, R ^a  

^a UNIVERSITY OF BOLOGNA   (Italy)

^b STMICROELECTRONICS   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

INSTRUCTION MEMORY; INSTRUCTION SET; OPEN-SOURCE; POWER SUPPLY; SOFTWARE APPLICATIONS; STANDARD CELL; SYSTEM ON CHIP DESIGN; VERY LONG INSTRUCTION WORDS;

APPLICATION PROGRAMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

MICROPROCESSOR CHIPS;

EID: 0042697360     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. D.Patterson,J.Hennessy, Computer Architecture: A Quantitative Approach, Morgan Kaufmann, 1991.
2. G.Kean, J.Heinrich, MIPS Rise Architecture, Prentice Hall, 1994
3. European Space Agency, LEON-1 Processor Model http://www.estec.esa.nl/ wsmwww/leon
4. L.Lavagno, C.Passerone, A.LaRosa, Private communication
5. M.Sergio, N.Manaresi, M.Tartagni, R.Canegallo, R.Guerrieri, A SOC for Pressure-Sensitive Fabric, Custom Integrated Circuits Conference, 2001