On the set of target path delay faults in sequential subcircuits of LUT-based FPGAs

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2438 LNCS, Issue , 2002, Pages 596-606

  Krasniewski, Andrzej ^a  

^a WARSAW UNIVERSITY OF TECHNOLOGY   (Poland)

Author keywords

[No Author keywords available]

Indexed keywords

DELAY CIRCUITS; ECONOMIC AND SOCIAL EFFECTS; RECONFIGURABLE ARCHITECTURES; TESTING;

LOGICAL PATHS; PATH DELAY FAULT; SUB-CIRCUITS; TEST PROCEDURES; TESTABILITY; TRADE OFF;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 79955154748     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-46117-5_62     Document Type: Conference Paper

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