Evaluation of the quality of testing path delay faults under restricted input assumption

Proceedings - 9th IEEE International On-Line Testing Symposium, IOLTS 2003

Volumn , Issue , 2003, Pages 168-170

  Krasniewski, A ^a  

^a WARSAW UNIVERSITY OF TECHNOLOGY   (Poland)

Author keywords

Boolean functions; Circuit faults; Circuit testing; Crosstalk; Field programmable gate arrays; Integrated circuit noise; Logic devices; Propagation delay; System testing; Working environment noise

Indexed keywords

BOOLEAN FUNCTIONS; CROSSTALK; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); LOGIC DEVICES;

CIRCUIT FAULTS; CIRCUIT TESTING; INTEGRATED CIRCUIT NOISE; PROPAGATION DELAYS; SYSTEM TESTING; WORKING ENVIRONMENT;

INTEGRATED CIRCUIT TESTING;

EID: 84944067501     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/OLT.2003.1214393     Document Type: Conference Paper

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