Static and high-frequency behavior and performance of Schottky-barrier p-MOSFET devices

IEEE Transactions on Electron Devices

Volumn 54, Issue 10, 2007, Pages 2796-2802

  Pearman, Dominic J ^a   Pailloncy, Guillaume ^b   Raskin, Jean Pierre ^b   Larson, John M ^c   Snyder, John P ^c   Parker, Evan H C ^a   Whall, Terence E ^a  

^a UNIVERSITY OF WARWICK   (United Kingdom)

^b UNIVERSITÉ CATHOLIQUE DE LOUVAIN   (Belgium)

^c Spinnaker Semiconductor   (United States)

Author keywords

Annealing; ColdFET; Electrostatic measurement; Microwave measurements; MOSFETs; Scattering parameter measurement; Schottky barriers; Schottky barrier metal source MOSFET; Semiconductor devices

Indexed keywords

ANNEALING; ELECTRIC CURRENTS; ELECTROSTATICS; MICROWAVE MEASUREMENT; SCATTERING PARAMETERS; SCHOTTKY BARRIER DIODES; SILICON WAFERS; TRANSCONDUCTANCE;

COLDFET; ELECTROSTATIC MEASUREMENT; RADIO-FREQUENCY;

MOSFET DEVICES;

EID: 35148843643     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2007.904985     Document Type: Article

References (25)

1. M. P. Lepselter and S. M. Sze, "An insulated-gate field-effect transistor using Schottky barrier contacts as source and drain," Proc. IEEE, vol. 56, no. 8, pp. 1400-1402, Aug. 1968.
2. C. J. Koeneke, S. M. Sze, R. M. Levin, and E. Kinsbron, "Schottky MOSFET for VLSI," in IEDM Tech. Dig., 1981, pp. 466-469.
3. J. R. Tucker, C. Wang, and P. S. Carney, "Silicon field-effect transistor based on quantum tunneling," Appl. Phys. Lett., vol. 65, no. 5, pp. 618-620, Aug. 1994.
4. T = 280 GHz," IEEE Electron Device Lett., vol. 25, no. 4, pp. 220-222, Apr. 2004.
5. J. M. Larson and J. Snyder, "Overview and status of metal S/D Schottky-barrier MOSFET technology," IEEE Trans. Electron Devices vol. 53, no. 5, pp. 1048-1058, May 2006.
6. Semiconductor Industry Association, International Technology Roadmap for Semiconductors, SIA, 2003.
7. D. A. Antoniadis. (2001, Jan.). Well-Tempered, Bulk-Si NMOSFET Device Home Page. [Online]. Available: http://www-mtl.mit.edu/ researchgroups/Well/
8. G. Pailloncy and J.-P. Raskin, "New de-embedding technique based on Cold-FET measurement," in Proc. EUMIC, 2006, pp. 460-463.
9. E. Dubois and G. Larrieu, "Measurement of low Schottky barrier heights applied to metallic source/drain metal-oxide-semiconductor field effect transistors," J. Appl. Phys., vol. 96, no. 1, pp. 729-737, Jul. 2004.
10. Y. Taur and H. Ning, Fundamentals of Modern VLSI Devices. Cambridge, U.K.: Cambridge Univ. Press, 1998.
11. Y. Tsividis, Operation and Modeling of the MOS Transistor. New York: McGraw-Hill, 1999.
12. D. Barlage, R. Arghavani, G. Dewey, M. Doczy, B. Doyle, J. Kavalieros, A. Murthy, B. Roberds, P. Stokley, and R. Chan, High-Frequency Response of 100 nm Integrated CMOS Transistors With High-K Gate Dielectrics. Hillsboro, OR: Components Res. Logic Technol. Develop., Intel Corp., 2001, p. 40.
13. J. N. Burghartz, M. Hargrove, C. S. Webster, R. A. Groves, M. Keene, K. A. Jenkins, R. Logan, and E. Nowak, "RF potential of a 0.18-mm CMOS logic device technology," IEEE Trans. Electron Devices, vol. 47, no. 4, pp. 864-870, Apr. 2000.
14. A. Chatterjee, J. Yoon, S. Zhao, S. Tang, K. Sadra, S. Crank, H. Mogul, R. Aggarwal, B. Chatterjee, S. Lytle, C. T. Lin, K. D. Lee, J. Kim, Q. Z. Hong, T. Kim, L. Olsen, M. Quevedo-Lopez, K. Kirmse, G. Zhang, C. Meek, D. Aldrich, H. Mair, M. Mehrotra, L. Adam, D. Mosher, J. Y. Yang, D. Crenshaw, B. Williams, J. Jacobs, M. Jain, J. Rosal, T. Houston, J. Wu, N. S. Nagaraj, D. Scott, S. Ashburn, and A. Tsao, "A 65 nm CMOS technology for mobile and digital signal processing applications," in IEDM Tech. Dig., 2004, pp. 665-668.
15. T. Hashimoto, Y. Nonaka, T. Saito, K. Sasahar, T. Tominari, K. Sakai, K. Tokunaga, T. Fujiwara, S. Wada, T. Udo, T. Jinbo, K. Washio, and H. Hosoe, "Integration of a 0.13-mm CMOS and a high performance self-aligned SiGe HBT featuring low base resistance," in IEDM Tech. Dig., 2002, pp. 779-782.
16. T. C. Holloway, G. A. Dixit, D. T. Grider, S. P. Ashburn, R. Aggarwal, A. Stub, X. Zhang, G. Misium, A. L. Esquivel, M. Jain, S. Madan, T. Breedijk, A. Singh, G. Thakar, G. Shinn, B. Riemenschneider, S. O'Brien, D. Frystak, J. Kittl, A. Amerasekera, S. Aur, P. Nicollian, D. Aldrich, and B. Eklund, "0.18 μm CMOS technology for high-performance, low-power, and RF applications," in VLSI Symp. Tech. Dig., 1997, p. 13.
17. T," in IEDM Tech. Dig., 1992, pp. 1012-1014.
18. T. Ohguro, E. Morifuji, M. Saito, M. Ono, T. Yoshitomi, H. S. Momose, N. Ito, and H. Iwai, "0.2 μm analog CMOS with very low noise figure at 2 GHz operation," in VLSI Symp. Tech. Dig., 1996, pp. 132-133.
19. M. Saito, M. Ono, R. Fujimoto, C. Takahashi, H. Tanimoto, N. Ito, T. Ohguro, T. Yoshitomi, H. S. Momose, and H. Iwai, "Advantage of small geometry silicon MOSFETs for high-frequency analog applications under low power supply voltage of 0.5 V," in VLSI Symp. Tech. Dig., 1995, pp. 71-72.
20. M. Saito, M. Ono, R. Fujimoto, H. Tanimoto, N. Ito, T. Yoshitomi, T. Ohguro, H. S. Momose, and H. Iwai, "0.15 μm RF CMOS technology compatible with logic CMOS for low-voltage operation," IEEE Trans. Electron Devices, vol. 45, no. 3, pp. 737-742, Mar. 1998.
21. Y. Taur, S. Wind, Y. J. Mii, Y. Lii, D. Moy, K. A. Jenkins, C. L. Chen, P. J. Coane, D. Klaus, J. Bucchignano, M. Rosenfield, M. G. R. Thomson, and M. Polcari, "High performance 0.1 μm CMOS devices with 1.5 V power supply," in IEDM Tech. Dig, 1993, pp. 127-130.
22. T. Yamamoto, A. Tanabe, M. Togo, A. Furukawa, and T. Mogami, "High-frequency characteristics and its dependence on parasitic components in 0.1 μm Si-MOSFETs," in VLSI Symp. Tech. Dig., 1996, pp. 136-137.
23. V. Ferlet-Cavrois, C. Marcandella, O. Musseau, J. L. Leray, J. L. Pelloire, F. Martin, S. Kolev, and D. Pasquet, "High-frequency performances of a partially depleted 0.18-μm SOI/CMOS technology at low supply voltage-influence of parasitic elements," IEEE Electron Device Lett., vol. 19, no. 7, pp. 265-267, Jul. 1998.
24. max with dual offset-implanted source/drain extension structure for RF/analog and logic applications," in IEDM Tech. Dig., 2001, pp. 219-222.
25. max, 90-nm SOI CMOS SoC technology with low-power millimeter-wave digital and RF circuit capability," in VLSI Symp. Tech. Dig., 2004, pp. 98-99.