200 MM germanium-on-insulator (GEOI) structures realized from epitaxial wafers using the smart cut™ technology

Proceedings - Electrochemical Society

Volumn PV 2005-02, Issue , 2005, Pages 78-88

  Deguet, C ^a   Dechamp, J ^a   Morales, C ^a   Charvet, A M ^a   Clavelier, L ^a   Loup, V ^a   Hartmann, J M ^a   Kernevez, N ^a   Campidelli, Y ^b   Allibert, F ^c   Richtarch, C ^c   Akatsu, T ^c   Letertre, F ^c  

^a CEA LETI   (France)

^b STMICROELECTRONICS   (France)

^c PARC TECHNOLOGIQUE DES FONTAINES   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; EPITAXIAL GROWTH; MICROELECTROMECHANICAL DEVICES; MICROELECTRONICS; NANOTECHNOLOGY;

DISLOCATION DENSITY; NANOELECTRONICS; SEMICONDUCTOR APPLICATIONS;

TRANSISTORS;

EID: 31844432924     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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