80nm Self-aligned complementary I-MOS using double sidewall spacer and elevated drain structure and its applicability to amplifiers with high linearity

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2004, Pages 203-206

  Choi, Woo Young ^a   Song, Jae Young ^a   Choi, Byung Yong ^a   Lee, Jong Duk ^a   Park, Young June ^a   Park, Byung Gook ^a  

^a Seoul National University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; ELECTROMETERS; MOSFET DEVICES; QUANTUM THEORY; SEMICONDUCTING SILICON; SILICA; THRESHOLD VOLTAGE;

ELECTRONIC CURRENTS; ELEVATED DRAIN STRUCTURES; GATE OXIDES; TUNNELING JUNCTION;

MOS CAPACITORS;

EID: 21644469564     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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2. K. Gopalakrishnan, P. B. Griffin, and J. D. Plummer, "I-MOS: a novel semiconductor device with a subthreshold slope lower than kT/q," in IEEE Int. Electron Devices (IEDM) Tech. Dig., pp. 289-292, 2002.
3. Woo Young Choi, Dong-Soo Woo, Byung Yong Choi, Jong Duk Lee, and Byung-Gook Park, "A Novel biasing scheme for the I-MOS (Impact-Ionization MOS)," in IEEE 2004 Silicon Nanoelectronics Workshop, pp. 61-62, 2004.
4. Woo Young Choi, Byung Yong Choi, Dong-Soo Woo, Jong Duk Lee, and Byung-Gook Park, "A new fabrication method for self-aligned nanoscale I-MOS (Impact-ionization MOS)," in 62nd Annual Device Research Conference, pp. 211-212, 2004.
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