Statistical timing analysis in the presence of signal-integrity effects

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 26, Issue 10, 2007, Pages 1873-1877

  Kahng, Andrew B ^a   Liu, Bao ^a   Xu, Xu ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Design; Reliability; Verification

Indexed keywords

CIRCUIT SIMULATION; CROSSTALK; DESIGN; ELECTRIC DELAY LINES; PROBABILISTIC LOGICS; RELIABILITY; VERIFICATION;

CROSSTALK AGGRESSOR SIGNALS; SIGNAL INTEGRITY EFFECTS; SIGNAL PROPAGATION DELAY VARIATIONS; STATIC TIMING ANALYZERS; STATISTICAL TIMING ANALYSIS;

SIGNAL ANALYSIS;

EID: 34748862290     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2007.895771     Document Type: Article

References (22)

1. A. Agarwal, D. Blaauw, V. Zolotov, and S. Vrudhula, "Statistical timing analysis using bounds," in Proc. Des. Autom. Test Eur., 2003, pp. 62-68.
2. A. Agarwal, F. Dartu, and D. Blaauw, "Statistical gate delay model considering multiple input switching," in Proc. Des. Autom. Conf., 2004, pp. 658-663.
3. Berkeley Predictive Technology Model [Online]. Available: http://wwwdevice.eecs.berkeley.edu/~ptm/
4. H. Chang and S. S. Sapatnekar, "Statistical timing analysis considering spatial correlations using a single PERT-like traversal," in Proc. Int. Conf. Comput.-Aided Des., 2003, pp. 621-625.
5. J. F. Croix and D. F. Wang, "Blade and razor: Cell and interconnect delay analysis using current-based models," in Proc. Des. Autom. Conf., 2004, pp. 386-389.
6. P. D. Gross, R. Arunachalam, K. Rajagopal, and L. T. Pileggi, "Determination of worst-case aggressor alignment for delay calculation," in Proc. Int. Conf. Comput.-Aided Des., 1998, pp. 212-219.
7. V. Khandelwal and A. Srivastava, "A general framework for accurate statistical timing analysis considering correlations," in Proc. Des. Autom. Conf., 2005, pp. 89-94.
8. A. B. Kahng, B. Liu, and X. Xu, "Statistical gate delay calculation with crosstalk alignment consideration'," in Proc. Great Lakes Symp. VLSI, 2006, pp. 223-228.
9. A. B. Kahng, B. Liu, and X. Xu, "Statistical crosstalk aggressor alignment aware interconnect delay calculation," in Proc. Syst. Level Interconnect Prediction, 2006, pp. 91-97.
10. H. Liu, A. Singhee, R. A. Rutenbar, and L. R. Carkey, "Remembrance of circuits past: Macromodeling by data mining in large analog design spaces," in Proc. Des. Autom. Conf., 2002, pp. 437-442.
11. J. D. Ma and R. A. Rutenbar, "Interval-valued reduced order statistical interconnect modeling," in Proc. Int. Conf. Comput.-Aided Des., 2004, pp. 460-467.
12. F. N. Najm and N. Menezes, "Statistical timing analysis based on a timing yield model," in Proc. Des. Autom. Conf., 2004, pp. 460-465.
13. A. Odabasioglu, M. Celik, and L. T. Pileggi, "PRIMA: Passive reducedorder interconnect macromodeling algorithm," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 17, no. 8, pp. 645-654, Aug. 1998.
14. M. Orshansky and A. Bandyopadhyay, "Fast statistical timing analysis handling arbitrary delay correlations," in Proc. Des. Autom. Conf., 2004, pp. 337-342.
15. M. Orshansky and K. .Keutzer, "A general probabilistic framework for worst case timing analysis," in Proc. Des. Autom. Conf., 2002, pp. 556-561.
16. M. Orshansky, L. Milor, P. Chen, K. Keutzer, and C. Hu, "Impact of spatial intrachip gate length variability on the performance of high-speed digital circuits," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 21, no. 5, pp. 544-553, May 2002.
17. M. Orshansky, W.-S. Wang, G. Xiang, and V. Kreinovich, "Interval-based robust statistical techniques for non-negative convex functions with applications to timing analysis of computer chips," in Proc. Reliable Eng. Comput., 2006, pp. 1645-1649.
18. D. Sinha and H. Zhou, "A unified framework for statistical timing analysis with coupling and multiple input switching," in Proc. Int. Conf. Comput.-Aided Des., 2005, pp. 837-843.
19. S. Sirichotiyakul, D. Blaauw, C. Oh, R. Levy, V. Zolotov, and J. Zuo, "Driver modeling and alignment for worst-case delay noise," in Proc. Des. Autom. Conf., 2001, pp. 720-725.
20. M. S. Srivastava, Methods of Multivariate Statistics. New York: Wiley-Interscience, 2002.
21. S. K. Tiwary and R. A. Rutenbar, "Scalable trajectory methods for on-demand analog macromodel extraction," in Proc. Des. Autom. Conf., 2005, pp. 403-408.
22. C. Visweswariah, K. Ravindran, K. Kalafala, S. G. Walker, and S. Narayan, "First-order incremental block-based statistical timing analysis," in Proc. Des. Autom. Conf., 2004, pp. 331-336.