Rapid characterization of threshold voltage fluctuation in MOS devices

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 2007, Pages 74-77

  Agarwal, Kanak ^a   Nassif, Sani ^a   Liu, Frank ^a   Hayes, Jerry ^a   Nowka, Kevin ^a  

^a IBM   (United States)

Author keywords

MOSFET; Process variation; Random dopant fluctuation; Test array; Threshold voltage

Indexed keywords

CHARACTERIZATION; DOPING (ADDITIVES); ELECTRIC CURRENTS; MICROPROCESSOR CHIPS; SILICON ON INSULATOR TECHNOLOGY; THRESHOLD VOLTAGE;

PROCESS VARIATION; RANDOM DOPANT FLUCTUATION; TEST ARRAYS; VOLTAGE SHIFT;

MOS DEVICES;

EID: 34548841100     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICMTS.2007.374458     Document Type: Conference Paper

References (11)

1. M. Qrshansky, L. Milor, P. Chen, K. Keutzer, C. Hu, "Impact of systematic spatial intra-chip gate length variability on performance of high-speed digital circuits", ICCAD 2000, pp. 62-67.
2. V. Mehrotra et al. "A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance", DAC, 2000, pp. 172-175.
3. B. Stine, D. Boning, J. Chung, "Analysis and decomposition of spatial variation in integrated circuit processes and devices", IEEE Trans on Semiconductor Manufacturing, 1997, pp. 24-41.
4. R.W. Keyes, "The impact of randomness in the distribution of impurity Atoms cm FET threshold", Journal of Applied Physics, 1975, pp. 251-259.
5. X. Tang, V. De, J. Meindl, "Intrinsic MOSFET parameter placement due to random placement", IEEE Trans on VLSI, 1997, pp. 369-376.
6. M. Bhushan, M. Ketchen, S. Polonsky, A. Gattiker, "Ring oscillator based technique for measuring variability statistics", Intl Conf on Microelectronic test structures, 2006, pp. 87-92.
7. K. Terada, M. Eimitsu, "A test circuit for measuring MOSFBT threshold voltage mismatch", Intl Conf on Microelectronic Test Structures, 2003, pp. 227-231.
8. T. Mizuno, J. Okamura, A. Toriumi, "Experimental study of threshold voltage: fluctuation due to statistical variation of channel dopant number in MOSFETs", IEEE Trans on Electron Devices, 1194, pp. 2216-2221.
9. A. Keshavarzi et al., "Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage", Intl Symp on Low Power Electronic Design, 2005, pp. 26-29.
10. K. Agarwal et al., "A test structure for characterizing local device mismatches", Symp on VLSI Circuits, 2006, pp. 82-83.
11. E. Leobandung et al., "High-performance 65 nm SOI technology with dual stress liner and low capacitance SRAM ceil", Symp on VLSI Technology, 2005, pp. 126-127.