메뉴 건너뛰기




Volumn , Issue , 2007, Pages 1069-1072

A study on impact of leakage current on dynamic power

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTATION THEORY; COMPUTER SIMULATION; ELECTRIC NETWORK ANALYSIS; MATHEMATICAL MODELS; SWITCHING;

EID: 34548832569     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iscas.2007.378194     Document Type: Conference Paper
Times cited : (7)

References (15)
  • 1
    • 34548830334 scopus 로고    scopus 로고
    • International Roadmap for Semiconductors
    • http://www.itrs.net/Common/2004Update/2004_03_PI.DS.pdf: International Roadmap for Semiconductors
  • 2
    • 0042090415 scopus 로고    scopus 로고
    • Accurate Estimation of Total Leakage Current in Scaled CMOS Logic Circuits Based on Compact Current Modeling
    • S. Mukhopadhyay, A. Raychowdhury, K. Roy, "Accurate Estimation of Total Leakage Current in Scaled CMOS Logic Circuits Based on Compact Current Modeling," DAC 2003, Proceedings, pp. 169-174
    • DAC 2003, Proceedings , pp. 169-174
    • Mukhopadhyay, S.1    Raychowdhury, A.2    Roy, K.3
  • 3
    • 33646904250 scopus 로고    scopus 로고
    • Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits
    • S. Mukhopadhyay, S. Bhunia, K. Roy, "Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits," DATE 2005, Proceedings, pp. 224-229 Vol. 1
    • DATE 2005, Proceedings , vol.1 , pp. 224-229
    • Mukhopadhyay, S.1    Bhunia, S.2    Roy, K.3
  • 4
    • 1542359168 scopus 로고    scopus 로고
    • Efficient Techniques for Gate Leakage Estimation
    • R. Brown, J. Burns, A. Devgan, R. Brown, "Efficient Techniques for Gate Leakage Estimation," ISLPED '03, pp. 100-103
    • ISLPED '03 , pp. 100-103
    • Brown, R.1    Burns, J.2    Devgan, A.3    Brown, R.4
  • 5
    • 0034453479 scopus 로고    scopus 로고
    • BSIM4 Gate Leakage Model Including Source-Drain Partition
    • C. Hu et al., "BSIM4 Gate Leakage Model Including Source-Drain Partition," International Electron Device Meeting 2000, pp. 815-818
    • (2000) International Electron Device Meeting , pp. 815-818
    • Hu, C.1
  • 6
    • 34548858872 scopus 로고    scopus 로고
    • C. Hu et al., BSIM4.5.0 MOSFET Model, User's Manual, 2004
    • C. Hu et al., "BSIM4.5.0 MOSFET Model", User's Manual, 2004
  • 7
    • 17644373135 scopus 로고    scopus 로고
    • Circuit-based preprocessing of ILP and its applications in leakage minimization, and power estimation
    • D. Chai, A. Kuehlmann, "Circuit-based preprocessing of ILP and its applications in leakage minimization, and power estimation", International Conference on Computer Design 2004, pp. 387-392
    • (2004) International Conference on Computer Design , pp. 387-392
    • Chai, D.1    Kuehlmann, A.2
  • 8
    • 34548844628 scopus 로고    scopus 로고
    • SIS: Logic Synthesis of Synchronous and Asynchronous Sequential Circuit program, UC Berkeley
    • SIS: Logic Synthesis of Synchronous and Asynchronous Sequential Circuit program, UC Berkeley
  • 9
    • 0042921255 scopus 로고    scopus 로고
    • Y. Cao, M. Orhansky, T. Sato, D. Sylvester, C. Hu et al., Spice up your MOSFET Modeling, Circuits and Device Magazine, IEEE 2003, pp. 17-23 19, Issue 4
    • Y. Cao, M. Orhansky, T. Sato, D. Sylvester, C. Hu et al., "Spice up your MOSFET Modeling", Circuits and Device Magazine, IEEE 2003, pp. 17-23 Vol. 19, Issue 4
  • 10
    • 0042196141 scopus 로고    scopus 로고
    • D. Lee, W. Kwong, D. Blaauw, D. Sylvester, Simultaneous Subthreshold and Gate-Oxide Tunneling Leakage Current Analysis in Nanometer CMOS Design, ISQED '03, pp. 287-292
    • D. Lee, W. Kwong, D. Blaauw, D. Sylvester, "Simultaneous Subthreshold and Gate-Oxide Tunneling Leakage Current Analysis in Nanometer CMOS Design", ISQED '03, pp. 287-292
  • 11
    • 0030146154 scopus 로고    scopus 로고
    • Power Dissipation Analysis and Optimization of Deep Submicron CMOS Digital Circuits
    • May
    • R. Gu, M. Elmasry, "Power Dissipation Analysis and Optimization of Deep Submicron CMOS Digital Circuits", IEEE Journal of Solid-State Circuits, pp. 707-714, Vol. 31 No. 5, May 1996
    • (1996) IEEE Journal of Solid-State Circuits , vol.31 , Issue.5 , pp. 707-714
    • Gu, R.1    Elmasry, M.2
  • 12
    • 16244371744 scopus 로고    scopus 로고
    • W. Hung, Y. Xie, N. Vijakrishnan, M. Kandemir, M.J. Irwin, Y. Tsai, Total Power Optimization through Simultaneously Multiple-VDD Multiple-VTH Assignment and Device Sizing with Stack Forcing, ISLPED '04, pp. 144-149
    • W. Hung, Y. Xie, N. Vijakrishnan, M. Kandemir, M.J. Irwin, Y. Tsai, "Total Power Optimization through Simultaneously Multiple-VDD Multiple-VTH Assignment and Device Sizing with Stack Forcing", ISLPED '04, pp. 144-149


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.