Modeling and analysis of loading effect in leakage of nano-scaled bulk-CMOS logic circuits

Proceedings -Design, Automation and Test in Europe, DATE '05

Volumn I, Issue , 2005, Pages 224-229

  Mukhopadhyay, Saibal ^a   Bhunia, Swarup ^a   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC LOADS; ELECTRIC POTENTIAL; LEAKAGE CURRENTS; TOPOLOGY; TRANSISTORS; TUNNEL JUNCTIONS;

CIRCUIT LEVEL INTERACTION; LEAKAGE POWER; REVERSE BIASED JUNCTIONS; TRANSISTOR STACKING;

LOGIC CIRCUITS;

EID: 33646904250     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2005.210     Document Type: Conference Paper

References (11)

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